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66AK2G12: DDR3L routing specification

Naoki Kawada
Guru 19890 points
Part Number: 66AK2G12


Hi,

My customer is now designing their custom board with 66AK2G12. Now they are checking DDR3L routing specifications described in the datasheet and has some questions:


1. It appeared that they could not meet the specification CARS33 in Table 7-11. CK and ADDR_CTRL Routing Specification. It suggests 125ps (max), but actually 175ps in their current design. Is this critical violation in routing requirement ?  Or, is this relaxed some, for example, "it is okay if they meets CARS31＋CARS33 < 625ps". Could you comment ?

2. They can`t understand what is actually specified by DRS35 in Table 7-12. Data Routing Specification. Could you please explain more details ? Is this allowed skew within a byte lane ? 

Best Regards,
NK

  • 0
    Guru 19890 points
    Sorry to rush you, but the customer would like to have your answers very soon...
    Thank you for your cooperation.

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Guru* 88330 points
    Naoki, are they adhering to the placement specifications? They should try to achieve cars33, otherwise,as the note says, they need to perform detailed signal integrity analysis of rise/fall time to confirm operation

    Yes, DRS35 is allowed byte skew within a byte lane.

    Regards,
    James
  • 0 in reply to JJD
    Guru 19890 points

    Hello James,

    Thank you for your quick reply. 

    CARS31 has a foot note (1):

    (1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
    rise time and fall time confirms desired operation.

    But CARS33 does not have this foot note. Can they extend the max value if they could validated the signal integrity ? 

    As i mentioned, they can`t meet CARS33 requirement. But CARS31 is easy for them to meet the spec. They are so appreciated if they could have a exception for CARS33 requirement, such as, CARS31 + CARS33 < 625ps. 

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    NK,

    CARS33 has a maximum length of 125ps which equates to about 750mils (18.75mm).  This is a generous amount of distance between 2 SDRAMs.  Why can't they meet this limit?  The arrangement of the SDRAMs needs to match the diagrams provided.  Please provide an image showing the SDRAM placement on the PCB.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points
    Hello Tom,

    Thanks for your reply. I`ll ask the customer if they could provide the image.

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    Guru 19890 points
    Hello Tom

    Thanks for all your support!
    I confirmed they could meet the requirements. I close the thread.

    Best Regards,
    NK