Tool/software: Linux
Hi Shravan,
I do not use cmem driver, and not access system diagnosis information in DSP.
Also I have checked that OPENVX_INCLUDE=no in my cfg.mk file.
I'm not sure which peripheral is used by DSP. Is there any document about hardware resource split in "ti_components"? (in addition <VisionSDK_Linux_DevelopmentGuide.pdf>)
I have check the DSP startup process, no special peripheral is used. so any ideas?
attachment some peripheral initialization in MLO:
void enable_vip_dss_clocks(void)
{
u32 reg;
/* Set the LCD channel 0 clock polatiry as falling edge */
//__raw_writel(0x80000, CTRL_CORE_SMA_SW_1);
/* enable CORE domain transitions */
//__raw_writel(0x2, CM_DSS_CLKSTCTRL);
/* enable power domain transitions (sw_wkup mode) */
__raw_writel(0x2, CM_VPE_CLKSTCTRL);
reg = __raw_readl(CM_L3INSTR_L3_MAIN_2_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_L3INSTR_L3_MAIN_2_CLKCTRL);
/* Enable IPU module peripherals */
reg = __raw_readl(CM_CAM_VIP1_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_CAM_VIP1_CLKCTRL);
reg = __raw_readl(CM_CAM_VIP2_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_CAM_VIP2_CLKCTRL);
reg = __raw_readl(CM_CAM_VIP3_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_CAM_VIP3_CLKCTRL);
reg = __raw_readl(CM_L3INSTR_L3_MAIN_2_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_L3INSTR_L3_MAIN_2_CLKCTRL);
#if 0
reg = __raw_readl(CM_L4PER_I2C1_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x2, CM_L4PER_I2C1_CLKCTRL);
reg = __raw_readl(CM_L4PER_I2C2_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x2, CM_L4PER_I2C2_CLKCTRL);
reg = __raw_readl(CM_L4PER_I2C3_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x2, CM_L4PER_I2C3_CLKCTRL);
reg = __raw_readl(CM_L4PER_I2C4_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x2, CM_L4PER_I2C4_CLKCTRL);
reg = __raw_readl(CM_IPU_I2C5_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x2, CM_IPU_I2C5_CLKCTRL);
#endif
reg = __raw_readl(CM_VPE_VPE_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_VPE_VPE_CLKCTRL);
/* enable DSS */
#if 0
reg = __raw_readl(CTRL_CORE_CONTROL_IO_2);
__raw_writel((reg | 0x1), CTRL_CORE_CONTROL_IO_2);
reg = __raw_readl(CM_DSS_DSS_CLKCTRL);
__raw_writel(((reg & ~0x00000003) | 0x00003F00 | 0x2), CM_DSS_DSS_CLKCTRL);
/* checking if DSS is enabled */
while ((__raw_readl(CM_DSS_DSS_CLKCTRL) & 0x00030000) != 0);
#endif
return;
}
/*
* If the remotecore binary expects any peripherals to be setup before it has
* booted, configure them here.
*
* These functions are left empty by default as their operation is usecase
* specific.
*/
u32 ipu1_config_peripherals(u32 core_id, struct rproc *cfg)
{
#if 1
u32 reg;
//u32 timer_reg = 0;
/* Enable Timer 9 used as timestamp provider for IPU1 */
reg = __raw_readl(CM_L4PER_TIMER9_CLKCTRL);
__raw_writel((reg & ~0x0F000003) | 0x00000002, CM_L4PER_TIMER9_CLKCTRL);
#endif
enable_vip_dss_clocks();
return 0;
}
u32 ipu2_config_peripherals(u32 core_id, struct rproc *cfg)
{
u32 reg;
reg = __raw_readl(CM_L4PER_GPIO2_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_L4PER_GPIO2_CLKCTRL);
reg = __raw_readl(CM_L4PER_GPIO7_CLKCTRL);
__raw_writel((reg & ~0x00000003)|0x1, CM_L4PER_GPIO7_CLKCTRL);
return 0;
}
u32 dsp1_config_peripherals(u32 core_id, struct rproc *cfg)
{
#if 1
u32 reg;
u32 timer_reg = 0;
/* Enable Timer 6 used as timestamp provider for DSP1 */
timer_reg = CM_IPU_TIMER6_CLKCTRL;
reg = __raw_readl(timer_reg);
__raw_writel((reg & ~0x0F000003) | 0x00000002, timer_reg);
#endif
return 0;
}
u32 dsp2_config_peripherals(u32 core_id, struct rproc *cfg)
{
#if 1
u32 reg;
u32 timer_reg = 0;
timer_reg = CM_IPU_TIMER5_CLKCTRL;
reg = __raw_readl(timer_reg);
__raw_writel((reg & ~0x0F000003) | 0x00000002, timer_reg);
#endif
return 0;
}
late-attach peripherals in Linux
/* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include "dra7-evm.dts" #define LATE_ATTACH(label) &label { ti,late-attach; ti,no-idle-on-init; ti,no-reset-on-init; } /* * Restrict the linux used EDMA requests to only 32 * Last 32 requests lines would be routed by the edma-xbar * to perform DMA for DSPs and IPUs */ &edma { dma-requests = <32>; }; /* * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000 * Page Table Address for IPU1 0xbfc00000 * Page Table Address for IPU2 0xbfc08000 * Page Table Address for DSP1 0xbfc10000 * Page Table Address for DSP2 0xbfc18000 */ &reserved_mem { latea_pagetbl: late_pgtbl@bfc00000 { reg = <0x0 0xbfc00000 0x0 0x100000>; no-map; status = "okay"; }; }; /* Uncomment below block to enable late attach for IPU2 */ LATE_ATTACH(ipu2); &ipu2 { /delete-property/ watchdog-timers; }; LATE_ATTACH(timer3); LATE_ATTACH(timer4); LATE_ATTACH(timer9); LATE_ATTACH(mmu_ipu2); /* Uncomment below block to enable late attach for IPU1 */ LATE_ATTACH(ipu1); &ipu1 { /delete-property/ watchdog-timers; }; LATE_ATTACH(timer11); LATE_ATTACH(timer7); LATE_ATTACH(timer8); LATE_ATTACH(mmu_ipu1); /* Uncomment below block to enable late attach for DSP1 */ LATE_ATTACH(dsp1); &dsp1 { /delete-property/ watchdog-timers; }; LATE_ATTACH(timer5); LATE_ATTACH(timer10); LATE_ATTACH(mmu0_dsp1); LATE_ATTACH(mmu1_dsp1); /* Uncomment below block to enable late attach for DSP2 */ LATE_ATTACH(dsp2); &dsp2 { /delete-property/ watchdog-timers; }; LATE_ATTACH(timer6); LATE_ATTACH(mmu0_dsp2); LATE_ATTACH(mmu1_dsp2); LATE_ATTACH(timer13); LATE_ATTACH(timer14); LATE_ATTACH(mailbox5); LATE_ATTACH(mailbox6); LATE_ATTACH(mailbox7); LATE_ATTACH(mailbox8); #define DISABLE_PRCM(label) &label { ti,no-idle; ti,no-reset-on-init; } DISABLE_PRCM(gpio2); DISABLE_PRCM(gpio7); LATE_ATTACH(gpio2); LATE_ATTACH(gpio7);
Regard
Jaye
