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VPBE Interrupt Content (dm6437)

Elric
Expert 1250 points

Hi,

I was tracing the interrupt code for dm6436 vpbe drivers, but now I am a little confused.

At the end of each frame, an interrupt occurs and DDC_VPBEIsr function is executed.

DDC_VPBEIsr is mainly in three parts, operations for interlaced mode, operations for progressive mode and callback operations.

So far it is ok. I am using interlaced mode.

It gets the venc field if it is odd or even, using LLC_getVencField. I suppose this is related to interlaced mode characteristics: the odd lines of a field is read first, and the even lines are read.

If this register field value is equal with the venc handler's field value;

and if the register field value is equal with odd field enum value, then DDC_VPBEUpdateFreeQueue is called for window planes.

else if the register field value is equal with even field enum value, then DDC_VPBEUpdateFbAdress is called for window planes.

Unfortunaletly I couldnt understand this logic. I think it calls the DDC_VPBEUpdateFbAdress on the even lines; because of  even lines are read hence the current frame is ended and the next frame shall be processed.

But why the free queue is used on the odd fields. Besides, why are there two queues such as active and free?

I think what I need is a document where I can read the vpbe interrupt and queue logic, how they work ext... But there is no document for this, I think.

I will be appreciated if you help me,

Thanks,

Erman

 

 

  • TI__Expert 4935 points

    Erman,

    Some fact:
    The frame buffer register of VPBE/VPFE is shadowed - which means that this register is latched or used by the hardware at the time of VSYNC. So even though the driver programs the register, it takes effect only after the next VSYNC.

    Below description explains how the driver manages the buffer for interlaced capture:

    Consider that you want to display buffers B1 and B2 in order. Assume B0 is the previous buffer displayed.

    When to program B1?
    Since the register is shadowed, buffer B1 should be programmed well before field 0 (even field). Hence this is written to the register at the previous VSYNC ISR i.e. at an odd field.

    When to take back the displayed buffer B1?
    The hardware will take B1 at the next VSYNC (even field). And after two fields, the buffer B1 would have been displayed by the hardware. So when we get the next even field we are safe to take away B1 if and only if B2 is already programmed in the register at the previous odd field. So the driver frees up the displayed buffer at even field.

    This is the typical life cycle of a single buffer. You can extend this logic when you have to program B2, B3 and so on. I have a picture to illustrate the same. But I couldn't upload the same in the forum.

    Hope this clarifies your doubts.

    Regards,
    Sivaraj R

  • in reply to Sivaraj R3681
    TI__Mastermind 41665 points

     

    Sivaraj R said:
    I have a picture to illustrate the same. But I couldn't upload the same in the forum.

    Just a FYI, if you have a picture, or any file, you can post it within your forum profile, than you can link it in your post. I just verified this was possible yesterday

  • in reply to Sivaraj R3681
    Expert 1250 points

    Thank you, Sivaraj. This is a good explanation along with the example picture.