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RTOS/TMS320C6655: TMS320C6655: Packet transmission problem with SRIO

kang seungpum
Prodigy 80 points
Part Number: TMS320C6655

Tool/software: TI-RTOS

Dear Champs,

I want to transmit 10K bytes through NWRITE. 

The system's SRIO spec has a lane width of X4 and a data rate of 20Gbps (5Gbps X 4lane)
It was tested with JTAG of DSP.

The following problem occurs when transmitting a packet with 256 bytes.
 
The interval between the first 32 packets is 1clock and there is no problem, 
but after that the interval between the packets becomes longer (monitored by the FPGA's chipscope).
Why is the gap between packets longer?

Thanks and Best Regards,
  • 0
    TI__Mastermind 43296 points
    Hi Kang,

    Are you using the SRIO driver from Processor SDK? Which type (blocking vs. non-blocking) of socket API are you using? If it's blocking socket, have you checked LSU status completion code in each Srio_sockSend ( ) call? The completion code is returned from the API.
    Also do you see the same issue with slower speed, e.g. 2.5Gbps?

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Prodigy 80 points

    Hi Garrett,

    Thanks for your response.

    The LSU status completion code is checked and the result is 0b000 - Transaction complete, No Errors(Posted/Non-posted)

    At 2.5Gbps, the same symptom occurred.
    At 1.25Gbps, the packet was normally sent without a long term interval.

    Could this symptom happen because JTAG emulator is slow?

    Thanks and Best Regards,
    SI.

  • 0 in reply to Garrett Ding
    Prodigy 80 points
    Hi Garrett,

    Thanks for your response.

    The LSU status completion code is checked and the result is 0b000 - Transaction complete, No Errors(Posted/Non-posted)

    At 2.5Gbps, the same symptom occurred.
    At 1.25Gbps, the packet was normally sent without a long term interval.

    Could this symptom happen because JTAG emulator is slow?

    Thanks and Best Regards,
    SI.
  • 0 in reply to kang seungpum
    TI__Mastermind 43296 points
    Hi SI.

    >>It was tested with JTAG of DSP.
    >>monitored by the FPGA's chipscope

    I am not clear how this is tested. Can you please elaborate it?

    Are the SRIO packets transferred between DSPs or DSP and FPGA? If it's the late case, did you checked FPGA side if any error status and can it sustain the higher throughput?

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Prodigy 80 points

    Hi Garrett,

    >>It was tested with JTAG of DSP.

    >> monitored by the FPGA's chipscope

    DSP of JTAG is used to program and debug in DSP.

    JTAG of FPGA s used to program the FPGA and identify the SRIO signal coming into the FPGA through the chipscope.

    >> Are the SRIO packets transferred between DSPs or DSP and FPGA?

    The SRIO's Packet transfers between the DSP and the FPGA.

    >> If it's the late case, did you checked FPGA side if any error status and can it sustain the higher throughput?

    error status unchecked

    Thanks and Best Regards,
    SI.

  • 0 in reply to kang seungpum
    TI__Mastermind 43296 points
    Hi SI.

    Were you able to check the FPGA side to find out if anything slows down the packet transmission? Or is it a false warning from chipscope of JTAG in FPGA ?

    Regards,
    Garrett