AM4372: AM437x's QSPI boot flow

Hi everyone,

When QSPI boot, which of (1) to (3) below is the specification of "Command"?

(1) Command uses D0 only, communicates using address, dummy, and data D0 to D4
(2) Commands, addresses, dummies, and data are communicated using D0 to D4
(3) Neither of the above

Looking at figure 3 of the following link, Command used D0 only.

http://ftm.futureelectronics.com/2014/09/nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems/

About this behavior, I could not understand even reading the AM437x TRM.

I have one more question.

As Quad Read Command (0x6B) is Fast Read I think that normal Wait is necessary
Therefore, I think that it is necessary to set the number of wait for QSPI as well.
What is the Dummy Cycle number of AM437x?
Is it necessary to select QSPI FLASH which operates without Dummy Cycle at 12 MHz?

Best regards,

Sasaki