OMAP-L138: Power consumption of a timer

Hi Nigel


>>The spreadsheet says for the Timer 0/1 frequency fields 'Program this field with the timer frequency in MHz (max value of 12MHz).'. What is this frequency? Is it the module frequency (in that case limiting to 12MHz seems odd) or the timer period as a frequency or something else?

It is essentially the output frequency or the frequency at which can have the timer input pin to toggle every cycle. The tests were instrumented to give an upper bound of maximum activity power, so we did with assuming period set to 0 , and max clock frequency where pin is toggling every cycle. The module clock frequency is somewhat baked in the cvdd power already , once you put an output frequency in the frequency field.


>>If the spreadsheet is configured for 'Typical - 456MHz' using the button at the bottom and then I set Timer 0 to have a frequency of 1MHz the spreadsheet says the timer takes 8.2mW that seems a lot considering there is no I/O and it is just counting up. It's more than a SPI device running at 27MHz, 100% utilisation. Is there a bug in the spreadsheet or does the timer really take this much power? Also entering anything below 12MHz results in the same power consumption of 8.2mW, when you enter 12MHz it jumps to 12.4mW.

Again think of this as as the worst case when timers are enabled in a potentially artificially high activity test - once the timer is doing something meaningful , it consumes ~ 8 mW and if you bump of the frequency some more it does increase by some extent , but that is mostly core logic driving data externally etc, so the increment is a bit non linear.

Is there a certain power goal you are trying to get to with this device and not meeting it or is this just some initial assessment on device power looking at the "estimation" tool?

Regards
Mukul

Hi Mukul,

Thanks for the quick reply.

This is for some initial assessment to estimate power consumption and therefore battery life. We will need the timers to provide system ticks to the DSP and ARM cores (possibly different millisecond rates) and also a system wide time counter. All of these will be internally clocked from the PLL and not drive any output pins. Can we assume that the power consumption for this configuration of timers will be significantly less than the spreadsheet implies? Is there a way to get a better estimate other than configuring a real device as we want it and then trying to measure it? 

Regards

Nigel