• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 387 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

bogoMIPS test - Why is dummy read assembly instruction needed?

Dan Ringger
Intellectual 1790 points

We are using a bogoMIPS test similar to the Linux Kernel to verify that our processor is setup to run at the desired frequency (which is currently 600 MHz).  During our initialization, before executing our bogoMIPS test, we write to the c1 Control Register in order to enable the C, I and M bits.  We noticed that we had to do a dummy read of the c1 Control Register after setting the c1 Control Register in order to achieve the maximum bogoMIPS number.  For example, below is the code that set the c1 Control Register.  The line comments state which line we added to get the proper value from our bogo MIPS test.  Why is this dummy read assembly instruction needed?

    clear_ctl:              .word   0x30003807

    set_ctl:                .word   0x00001807

 

    /* program the C bit in the control register */

    mrc p15, 0, r0, c1, c0, 0

    ldr     r1, clear_ctl

    bic     r0, r0, r1

    ldr     r1, set_ctl

    orr     r0, r0, r1

    mcr p15, 0, r0, c1, c0, 0

    mrc p15, 0, r0, c1, c0, 0   /* why do we have to execute a dummy read here? */

    isb

  • 0
    TI__Mastermind 41665 points

    I am guessing this is for OMAP35xx?

    I did some digging through the kernel and I do not see this particular code sequence you show, I do see a place where the control register is written to and than immediately read back around line 482 of arch/arm/boot/compressed/head.S, is this the Linux source you are referring to or are you referencing something else? Is there a particular kernel version you took this code sequence from?

    As to an actual why an extra read instruction is needed, this is hard to say, as this is more of an ARM specific question as opposed to a TI specific question, we might get a better answer asking ARM directly. I did some digging in the ARM documentation, and I see no reason you would have to read back the control register to enable the caching, the ARM TRM section 3.2.25 makes it seem you can read and write this register arbitrarily.