Dear All,
We have a technical HW question regarding the DM6467T EVM
We are using this as a ref design for our own board design and we do not understand the contribution of the following section
1256.Davincihd1080p_EVM_Schematics.pdf
We understand the power up sequence requirements of the DM6467T (1V2 then 1V8 and last 3V3 all to be completed within 200mS)
This is accomplished on the EVM by connecting the power good indication from each section to the Enable input of the next power supply.
Specifically only U43 above is needed to validate 1V2/1V3 core voltage stability since no power good indication provided directly from the PTH08T240W module.
POR_Resetn indication above can easily be derived from 3V3 power good indication without the need for above U41-U42 complex.
Since 3V3 power good only available after all 3 supplies are OK.
There is no much sense in above connection since by the time 3V3 is up, 1V8 was already guaranteed up by PS sequencing (power good dependencies) so U41 does nothing since 1V8 was already valid before.
If u just wanted some reset delay after powerup this can be easily implemented in EPLD.
Which brings us to another question, when 1V2 core is powered up, EPLD is still unpowered, hence we do not think it can guarantee holding the DM6467T at reset as is should during power up, it will only reset it after 1V8 and 3V3 power has gone up as well.
Are we missing something?
Any support would be appreciated.
Sincerely,
- Leor
