• Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 328 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Question about the proper capacitors to use for the TMS320DM6435 crystal circuit

KJ6946
Prodigy 50 points
Other Parts Discussed in Thread: TMS320DM6437, TMS320DM6435

I have a question about an apparent discrepancy between the crystal clock input option defined in the TMS320DM6435 spec (SPRS344C, June 2008) and the reference design TMS320DM6437 Evaluation Module. 

On page 3 of the schematic for the Evaluation Module from Spectrum Digital

http://c6000.spectrumdigital.com/evmdm6437/reve/files/EVMDM6437_Schematic.pdf

is crystal Y1 which is attached to capacitors C2 and C4 which are both 18pF.

Per the bill of materials

http://c6000.spectrumdigital.com/evmdm6437/reve/files/EVMDM6437_BML.pdf

Y1 is “Citizen America Corporation CS10-27.000MABJ-UT”.  The datasheet for this component

http://www.citizencrystal.com/images/pdf/m-cs10.pdf

lists the required load capacitance CL as being 18.0pF.

On page 158 of the TMS320DM6435 specification,

http://focus.ti.com/lit/ds/sprs344c/sprs344c.pdf

is an equation for computing the load capacitance.  Per that equation, using 18pF for C1 and C2, the computed load capacitance would then be 9pF but the requirement per the Citizen spec is for it to be 18pF.  But per the TI specification, it would appear that the correct values to use for C1 and C2 for a crystal that has an 18pF load requirement would be 36pF, not 18pF.

The Citizen web site also has a tech note

http://www.citizencrystal.com/images/pdf/tech-09.pdf

that talks a bit more about computing the load capacitance to include terms for the internal capacitance of the IC (in this case the 6435 which has a Cin and Cout of 5pF max in the spec) as well as stray PCB capacitance.  This tech note though doesn’t rigorously define just what they mean by these terms.  As an example, does ‘internal capacitance of IC’ refer to

-          The input capacitance of the input pin

-          The output capacitance of the output pin

-          The sum (i.e. parallel capacitive equivalent) of those two

-          The series equivalent of these two

I didn’t find any application note on the TI web site regarding the proper calculation of crystal load capacitance but the following article represents what I believe to be proper design practice in regards to computing load capacitance from the parameters for the two capacitors, the device input and output capacitance as well as the PCB trace capacitance.

http://www.crystekcrystals.com/crystal/appnotes/PierceGateLoadCap.pdf

Based on that article, the TI spec of 5pF and assuming a 0.22pF PCB capacitance for each leg between the 6435 and the crystal, one would then compute C1=C2=31pF which is in close agreement with the TI spec for the 6435 which does not take into account the input/output capacitance of the 6435 or the PCB trace.

Given all that, my questions are:

-          Why does the reference design call out use of 18pF capacitors?

-          Which is correct?  The 6435 specification which would say to use two 36pF capacitors or the Spectrum Digital schematic which says to use two 18pF capacitors or two 31pF capacitors which is based on including device and PCB parasitics?

-          Is there some reason that the TI specification for the 6435 does not even mention including the input and output capacitance of the device when computing CL?  The 5pF max is certainly not negligible compared to the 18pF capacitor that is on the evaluation module reference design schematic.

-          Does TI have any application notes that address the proper calculation of capacitor values and crystal load in general?

 Kevin Jennings

  • TI__Mastermind 41665 points

    The DM6437 EVM is not technically considered a reference design, particularly since it was designed early in the device's life cycle and was created to be ready to go as soon as possible as opposed to being highly optimized. However, the EVM does work and thus is often referenced for its schematics and BoM like this, so many customers use it as a reference design.

    Kevin Jennings said:
    Why does the reference design call out use of 18pF capacitors?

    This is a good question, I have had customers in the past bring up this same issue you put forward here, back then my only answer was that either the EVM design was wrong (though still functional) or that the crystal they actually used specified another value (the Citizen datasheet mentions you can specify the parameter).

    Kevin Jennings said:
    Which is correct?  The 6435 specification which would say to use two 36pF capacitors or the Spectrum Digital schematic which says to use two 18pF capacitors or two 31pF capacitors which is based on including device and PCB parasitics?

     

    My advice to prior customers (whom had no complaints as to the suggestion not working) was to follow the datasheet forumla for calculating their crystal values as opposed to copying the EVM verbatim.

    Kevin Jennings said:
      Does TI have any application notes that address the proper calculation of capacitor values and crystal load in general?

    Unfortunately the only mention of this within our documentation I know of is the datasheet which you have already referenced, though I can say that digging through google I found several places where crystal calculations gave the same forumulas that the datasheet suggests, which led me to believe that the EVM schematic is erroneous.

    Overall I agree that the EVM does not match the datasheet requirements, and that for your own design you should choose your capacitors per the datasheet. Even though the EVM does work (I have not come across any EVM crystal problems), it is far more advisable to follow the datasheet specifications, as I mentioned originally, the EVM was not meant to be a true reference design.