c6747 emifa asynchronous configuration : spurious pulses on CS4 and CS5

Frederic Leger

Other Parts Discussed in Thread: SYSCONFIG

Hi all,

I spent some time to make a gel file working on a custom board build around the C6747 DSP.

On EMIFA bus, we have 3 devices : an SRAM, (CS5) an FPGA (CS5) and a NOR Flash(CS2). each device have its own chip-select and configuraton.

All devices are asynchronous. SDRAM mode of EMIFA is not used neither configured.

I only configured the CE2CFG,CE3CFG,CE4CFG,CE5CFG and EMIFA_NANDFCR registers in the GEL file. I started with the GEL file of the OMAP_L137 DSK rev G.

NOR FLASH is responding fine on CS2 : CFI query is OK.

FPGA and SRAM are not responding. Using a scope, I have seen that both chip select got spurious pulses and can't be commanded.

After some reading in sprufl6e, i modified the registers concerning the SDRAM interface configuration of EMIFA => that changed the spurious pulses frequency.

when put in powerdown mode by wriiting 0x40000000 to the SDRAM config register: the spurious pulses disappear. But no CS4 and CS5 can be generated ....

if som

eone has an idea of what i could have missed in the configuration that could result in such a mess on CS4 and CS5 I would really appreciate !!!

Best regards,

Frederic

over 14 years ago

0 jc-ti over 14 years ago

TI__Mastermind 27585 points

I assume you mean SRAM is on CS4 and FPGA is on CS5, correct? Or are they using the same chip select for some reason?

So if you open the memory window in CCS and write data to 0x64000000, you dont see the CS, WE, or data pins change on the EMIFA bus? Can you make sure the pinmux registers are configured so that the CS3 CS4 and CS5 pins are selected for EMIFA mode?

It would help if you sent your EMIFA config register dump as well as the SYSCONFIG pinmux registers as well for us to look at. Thanks

Jeff

0 Frederic Leger over 14 years ago in reply to jc-ti

Intellectual 310 points

Thanks Jeff ! ! Exactly. pinmux registers were badly configured.

I didn't see that it was possible under the pinsetup utility to uncheck RAS and CAS of EMIFA to check CS4 and CS5 instead.

No more pulses now, but CS4 and CS5 are not responding when accessing 0x64000000 and 0x66000000 areas.

I am back reading sprufk4d...

Frederic

/*
MUX1 Pins:
EMB_SDCKE nEMB_CS[0] nEMB_CAS nEMB_RAS nEMB_WE EMB_BA[1] EMB_BA[0] EMB_A[0] EMB_A[1] EMB_A[2]
EMB_A[3] EMB_A[4] EMB_A[5] EMB_A[6] EMB_A[7] EMB_A[8] EMB_A[9] EMB_A[10] EMB_A[11] EMB_A[12]
EMB_D[31] EMB_D[30] EMB_D[29] EMB_D[28] EMB_D[27] EMB_D[26] EMB_D[25] EMB_D[24] EMB_D[23] EMB_D[22]
EMB_D[21] EMB_D[20] EMB_D[19] EMB_D[18] EMB_D[17] EMB_D[16] nEMB_WE_DQM[3] nEMB_WE_DQM[2] EMB_D[0] EMB_D[1]
EMB_D[2] EMB_D[3] EMB_D[4] EMB_D[5] EMB_D[6] EMB_D[7] EMB_D[8] EMB_D[9] EMB_D[10] EMB_D[11]
EMB_D[12] EMB_D[13] EMB_D[14] EMB_D[15] nEMB_WE_DQM[1] nEMB_WE_DQM[0] UART0_RXD UART0_TXD EMA_D[0] EMA_D[1]
EMA_D[2] EMA_D[3] EMA_D[4] EMA_D[5] EMA_D[6] EMA_D[7] EMA_D[8] EMA_D[9] EMA_D[10] EMA_D[11]
EMA_D[12] EMA_D[13] EMA_D[14] EMA_D[15] EMA_A[0] EMA_A[1] EMA_A[2] EMA_A[3] EMA_A[4] EMA_A[5]
EMA_A[6] EMA_A[7] EMA_A[8] EMA_A[9] EMA_A[10] EMA_A[11] EMA_A[12] EMA_BA[1] EMA_BA[0] nEMA_WE
nEMA_CS[2] nEMA_CS[3] nEMA_OE nEMA_WE_DQM[1] nEMA_WE_DQM[0] EMA_WAIT[0]

MUX2 Pins:
EMB_CLK nUART0_CTS nUART0_RTS I2C1_SCL I2C1_SDA UART2_RXD UART2_TXD RMII_MHZ_50_CLK RMII_TXD[0] RMII_TXD[1]
RMII_TXEN RMII_CRS_DV RMII_RXD[0] RMII_RXD[1] RMII_RXER MDIO_CLK MDIO_D nEMA_CS[4] nEMA_CS[5]

MUX3 Pins:

MUX4 Pins:

MUX5 Pins:

/* Created using the Pin Setup Utility (Version: 1.0.663.14) */

#define PINMUX0_VALUE 0x11112100
#define PINMUX1_VALUE 0x11111111
#define PINMUX2_VALUE 0x11111111
#define PINMUX3_VALUE 0x11111111
#define PINMUX4_VALUE 0x11111111
#define PINMUX5_VALUE 0x11111111
#define PINMUX6_VALUE 0x11111111
#define PINMUX7_VALUE 0x22000111
#define PINMUX8_VALUE 0x20011022
#define PINMUX9_VALUE 0x00200002
#define PINMUX10_VALUE 0x22222220
#define PINMUX11_VALUE 0x00000022
#define PINMUX12_VALUE 0x00000000
#define PINMUX13_VALUE 0x11000000
#define PINMUX14_VALUE 0x11111111
#define PINMUX15_VALUE 0x11111111
#define PINMUX16_VALUE 0x11111111
#define PINMUX17_VALUE 0x20011111
#define PINMUX18_VALUE 0x11111012
#define PINMUX19_VALUE 0x00000001

0 Frederic Leger over 14 years ago in reply to Frederic Leger

Intellectual 310 points

These are the EMIFA configuration registers values :

Frederic

0 Frederic Leger over 14 years ago in reply to Frederic Leger

Intellectual 310 points

Hi Jeff.

My mistake : Everything is working fine now !!! Just a problem of scope config.

Thanks for your support ! The pinmux setting was wrong.

Frédéric

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c6747 emifa asynchronous configuration : spurious pulses on CS4 and CS5