Linux/TDA2E: Error while MLO Booting:

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index ceee1a7..ecfaf60 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -8,14 +8,17 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
-#include "dra7-evm-common.dtsi"
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
 
 / {
 	model = "TI DRA742";
 	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
 
+	chosen {
+		stdout-path = &uart1;
+		tick-timer = &timer2;
+	};
+
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x60000000>; /* 1536 MB */
@@ -30,34 +33,23 @@
 		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
 	};
 
-	evm_3v3_sw: fixedregulator-evm_3v3_sw {
+	mmc2_3v3: fixedregulator-mmc2 {
 		compatible = "regulator-fixed";
-		regulator-name = "evm_3v3_sw";
-		vin-supply = <&sysen1>;
+		regulator-name = "mmc2_3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
 
-	aic_dvdd: fixedregulator-aic_dvdd {
-		/* TPS77018DBVT */
-		compatible = "regulator-fixed";
-		regulator-name = "aic_dvdd";
-		vin-supply = <&evm_3v3_sw>;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
+	extcon_usb1: extcon_usb1 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
 	};
 
-	vmmcwl_fixed: fixedregulator-mmcwl {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcwl_fixed";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio5 8 0>;	/* gpio5_8 */
-		startup-delay-us = <70000>;
-		enable-active-high;
+	extcon_usb2: extcon_usb2 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
 	};
 
-
 	vtt_fixed: fixedregulator-vtt {
 		compatible = "regulator-fixed";
 		regulator-name = "vtt_fixed";
@@ -66,30 +58,234 @@
 		regulator-always-on;
 		regulator-boot-on;
 		enable-active-high;
-		vin-supply = <&sysen2>;
 		gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 	};
 };
 
 &dra7_pmx_core {
-	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
+	pinctrl-names = "default";
+	pinctrl-0 = <&vtt_pin>;
+
+	vtt_pin: pinmux_vtt_pin {
+		pinctrl-single,pins = <
+			0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
+			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
+		>;
+	};
+
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+			0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+		>;
+	};
+
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
+			0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
+		>;
+	};
+
+	mcspi1_pins: pinmux_mcspi1_pins {
+		pinctrl-single,pins = <
+			0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
+			0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
+			0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
+			0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
+			0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
+			0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
+		>;
+	};
+
+	mcspi2_pins: pinmux_mcspi2_pins {
+		pinctrl-single,pins = <
+			0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
+			0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+			0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+			0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
+		>;
+	};
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
+			0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
+			0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
+			0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
+		>;
+	};
+
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+			0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
+			0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
+			0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
+			0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
+		>;
+	};
+
+	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			/* this pin is used as a GPIO via mcasp */
-			0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
+			0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
+			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
 
-	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
+	qspi1_pins: pinmux_qspi1_pins {
 		pinctrl-single,pins = <
-			0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
-			0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
+			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
+			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
+			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
+			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
+			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
+			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
+			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
+			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
+			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 		>;
 	};
 
-	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
+	usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+			0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+
+	usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+			0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+                >;
+        };
+
+	nand_flash_x16: nand_flash_x16 {
+		/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+		 * So NAND flash requires following switch settings:
+		 * SW5.9 (GPMC_WPN) = LOW
+		 * SW5.1 (NAND_BOOTn) = HIGH */
 		pinctrl-single,pins = <
-			0x408   (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
-			0x40c   (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+			0x0 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0	*/
+			0x4 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1	*/
+			0x8 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2	*/
+			0xc 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3	*/
+			0x10	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4	*/
+			0x14	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5	*/
+			0x18	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6	*/
+			0x1c	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7	*/
+			0x20	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad8	*/
+			0x24	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad9	*/
+			0x28	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad10	*/
+			0x2c	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad11	*/
+			0x30	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad12	*/
+			0x34	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad13	*/
+			0x38	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad14	*/
+			0x3c	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad15	*/
+			0xd8	(PIN_INPUT_PULLUP  | MUX_MODE0)	/* gpmc_wait0	*/
+			0xcc	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_wen	*/
+			0xb4	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_csn0	*/
+			0xc4	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_advn_ale */
+			0xc8	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_oen_ren	 */
+			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x250 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txc.rgmii0_txc */
+			0x254 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txctl.rgmii0_txctl */
+			0x258 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_td3.rgmii0_txd3 */
+			0x25c (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txd2.rgmii0_txd2 */
+			0x260 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txd1.rgmii0_txd1 */
+			0x264 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txd0.rgmii0_txd0 */
+			0x268 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxc.rgmii0_rxc */
+			0x26c (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxctl.rgmii0_rxctl */
+			0x270 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd3.rgmii0_rxd3 */
+			0x274 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd2.rgmii0_rxd2 */
+			0x278 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd1.rgmii0_rxd1 */
+			0x27c (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd0.rgmii0_rxd0 */
+
+			/* Slave 2 */
+			0x198 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d12.rgmii1_txc */
+			0x19c (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d13.rgmii1_tctl */
+			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d14.rgmii1_td3 */
+			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d15.rgmii1_td2 */
+			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d16.rgmii1_td1 */
+			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d17.rgmii1_td0 */
+			0x1b0 (PIN_INPUT | MUX_MODE3)	/* vin2a_d18.rgmii1_rclk */
+			0x1b4 (PIN_INPUT | MUX_MODE3)	/* vin2a_d19.rgmii1_rctl */
+			0x1b8 (PIN_INPUT | MUX_MODE3)	/* vin2a_d20.rgmii1_rd3 */
+			0x1bc (PIN_INPUT | MUX_MODE3)	/* vin2a_d21.rgmii1_rd2 */
+			0x1c0 (PIN_INPUT | MUX_MODE3)	/* vin2a_d22.rgmii1_rd1 */
+			0x1c4 (PIN_INPUT | MUX_MODE3)	/* vin2a_d23.rgmii1_rd0 */
+		>;
+
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x250 (MUX_MODE15)
+			0x254 (MUX_MODE15)
+			0x258 (MUX_MODE15)
+			0x25c (MUX_MODE15)
+			0x260 (MUX_MODE15)
+			0x264 (MUX_MODE15)
+			0x268 (MUX_MODE15)
+			0x26c (MUX_MODE15)
+			0x270 (MUX_MODE15)
+			0x274 (MUX_MODE15)
+			0x278 (MUX_MODE15)
+			0x27c (MUX_MODE15)
+
+			/* Slave 2 */
+			0x198 (MUX_MODE15)
+			0x19c (MUX_MODE15)
+			0x1a0 (MUX_MODE15)
+			0x1a4 (MUX_MODE15)
+			0x1a8 (MUX_MODE15)
+			0x1ac (MUX_MODE15)
+			0x1b0 (MUX_MODE15)
+			0x1b4 (MUX_MODE15)
+			0x1b8 (MUX_MODE15)
+			0x1bc (MUX_MODE15)
+			0x1c0 (MUX_MODE15)
+			0x1c4 (MUX_MODE15)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_d.mdio_d */
+			0x240 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			0x23c (MUX_MODE15)
+			0x240 (MUX_MODE15)
+		>;
+	};
+
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+			0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
+			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
 		>;
 	};
 
@@ -427,6 +623,8 @@
 
 &i2c1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
 	clock-frequency = <400000>;
 
 	tps659038: tps659038@58 {
@@ -450,7 +648,7 @@
 					/* VDD_DSPEVE */
 					regulator-name = "smps45";
 					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1250000>;
+					regulator-max-microvolt = <1150000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -468,7 +666,7 @@
 					/* CORE_VDD */
 					regulator-name = "smps7";
 					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-max-microvolt = <1060000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -496,7 +694,6 @@
 					regulator-name = "ldo1";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
 					regulator-boot-on;
 				};
 
@@ -526,7 +723,6 @@
 					regulator-max-microvolt = <1050000>;
 					regulator-always-on;
 					regulator-boot-on;
-					regulator-allow-bypass;
 				};
 
 				ldoln_reg: ldoln {
@@ -545,46 +741,10 @@
 					regulator-max-microvolt = <3300000>;
 					regulator-boot-on;
 				};
-
-				/* REGEN1 is unused */
-
-				regen2: regen2 {
-					/* Needed for PMIC internal resources */
-					regulator-name = "regen2";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				/* REGEN3 is unused */
-
-				sysen1: sysen1 {
-					/* PMIC_REGEN_3V3 */
-					regulator-name = "sysen1";
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				sysen2: sysen2 {
-					/* PMIC_REGEN_DDR */
-					regulator-name = "sysen2";
-					regulator-boot-on;
-					regulator-always-on;
-				};
 			};
 		};
 	};
 
-	pcf_lcd: gpio@20 {
-		compatible = "nxp,pcf8575";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
 	pcf_gpio_21: gpio@21 {
 		compatible = "ti,pcf8575";
 		reg = <0x21>;
@@ -597,39 +757,52 @@
 		#interrupt-cells = <2>;
 	};
 
-	tlv320aic3106: tlv320aic3106@19 {
-		#sound-dai-cells = <0>;
-		compatible = "ti,tlv320aic3106";
-		reg = <0x19>;
-		adc-settle-ms = <40>;
-		ai3x-micbias-vg = <1>;		/* 2.0V */
-		status = "okay";
-
-		/* Regulators */
-		AVDD-supply = <&evm_3v3_sw>;
-		IOVDD-supply = <&evm_3v3_sw>;
-		DRVDD-supply = <&evm_3v3_sw>;
-		DVDD-supply = <&aic_dvdd>;
-	};
 };
 
 &i2c2 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
 	clock-frequency = <400000>;
+};
 
-	pcf_hdmi: gpio@26 {
-		compatible = "nxp,pcf8575";
-		reg = <0x26>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		p1 {
-			/* vin6_sel_s0: high: VIN6, low: audio */
-			gpio-hog;
-			gpios = <1 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "vin6_sel_s0";
-		};
-	};
+&i2c3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+	clock-frequency = <400000>;
+};
+
+&mcspi1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcspi1_pins>;
+};
+
+&mcspi2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcspi2_pins>;
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			      <&dra7_pmx_core 0x3e0>;
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
 };
 
 &mmc1 {
@@ -657,7 +830,7 @@
 
 &mmc2 {
 	status = "okay";
-	vmmc-supply = <&evm_3v3_sw>;
+	vmmc-supply = <&mmc2_3v3>;
 	bus-width = <8>;
 	max-frequency = <192000000>;
 	pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
@@ -673,12 +846,97 @@
 	cpu0-supply = <&smps123_reg>;
 };
 
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_pins>;
+
+	spi-max-frequency = <64000000>;
+	m25p80@0 {
+		compatible = "s25fl256s1","spi-flash";
+		spi-max-frequency = <76800000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first four physical blocks
+		 * for a valid file to boot and the flash here is
+		 * 64KiB block size.
+		 */
+		partition@0 {
+			label = "QSPI.SPL";
+			reg = <0x00000000 0x000010000>;
+		};
+		partition@1 {
+			label = "QSPI.SPL.backup1";
+			reg = <0x00010000 0x00010000>;
+		};
+		partition@2 {
+			label = "QSPI.SPL.backup2";
+			reg = <0x00020000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.SPL.backup3";
+			reg = <0x00030000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.u-boot";
+			reg = <0x00040000 0x00100000>;
+		};
+		partition@5 {
+			label = "QSPI.u-boot-spl-os";
+			reg = <0x00140000 0x00080000>;
+		};
+		partition@6 {
+			label = "QSPI.u-boot-env";
+			reg = <0x001c0000 0x00010000>;
+		};
+		partition@7 {
+			label = "QSPI.u-boot-env.backup1";
+			reg = <0x001d0000 0x0010000>;
+		};
+		partition@8 {
+			label = "QSPI.kernel";
+			reg = <0x001e0000 0x0800000>;
+		};
+		partition@9 {
+			label = "QSPI.file-system";
+			reg = <0x009e0000 0x01620000>;
+		};
+	};
+};
+
+&omap_dwc3_1 {
+	extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+	extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_pins>;
+};
+
 &elm {
 	status = "okay";
 };
 
 &gpmc {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x16>;
 	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
 	nand@0,0 {
 		reg = <0 0 4>;		/* device IO registers */
@@ -770,6 +1028,9 @@
 
 &mac {
 	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
 	dual_emac;
 };
 
@@ -784,3 +1045,17 @@
 	phy-mode = "rgmii";
 	dual_emac_res_vlan = <2>;
 };
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep", "active";
+	pinctrl-0 = <&dcan1_pins_sleep>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+	pinctrl-2 = <&dcan1_pins_default>;
+};
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e9eb8f0..4fc3985 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -906,7 +906,7 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
 			dma-names = "tx", "rx";
-			mmc-hs200-1_8v;
+			/*mmc-hs200-1_8v; BOOT_OPT */
 			mmc-ddr-1_8v;
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
index 9ca33a8..c201fef 100644
--- a/arch/arm/dts/dra71-evm.dts
+++ b/arch/arm/dts/dra71-evm.dts
@@ -365,6 +365,7 @@
 		lp8733_regulators: regulators {
 			lp8733_buck0_reg: buck0 {
 				/* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
+				compatible = "ti,lp873x-buck0";
 				regulator-name = "lp8733-buck0";
 				regulator-min-microvolt = <850000>;
 				regulator-max-microvolt = <1250000>;
@@ -375,6 +376,7 @@
 
 			lp8733_buck1_reg: buck1 {
 				/* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
+				compatible = "ti,lp873x-buck1";
 				regulator-name = "lp8733-buck1";
 				regulator-min-microvolt = <850000>;
 				regulator-max-microvolt = <1250000>;
@@ -385,6 +387,7 @@
 
 			lp8733_ldo0_reg: ldo0 {
 				/* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
+				compatible = "ti,lp873x-ldo0";
 				regulator-name = "lp8733-ldo0";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -393,6 +396,7 @@
 
 			lp8733_ldo1_reg: ldo1 {
 				/* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
+				compatible = "ti,lp873x-ldo1";
 				regulator-name = "lp8733-ldo1";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -410,6 +414,7 @@
 		lp8732_regulators: regulators {
 			lp8732_buck0_reg: buck0 {
 				/* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
+				compatible = "ti,lp873x-buck0";
 				regulator-name = "lp8732-buck0";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -420,6 +425,7 @@
 
 			LP8732_buck1_reg: buck1 {
 				/* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
+				compatible = "ti,lp873x-buck1";
 				regulator-name = "lp8732-buck1";
 				regulator-min-microvolt = <1350000>;
 				regulator-max-microvolt = <1350000>;
@@ -430,6 +436,7 @@
 
 			lp8732_ldo0_reg: ldo0 {
 				/* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
+				compatible = "ti,lp873x-ldo0";
 				regulator-name = "lp8732-ldo0";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -440,6 +447,7 @@
 
 			lp8732_ldo1_reg: ldo1 {
 				/* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
+				compatible = "ti,lp873x-ldo1";
 				regulator-name = "lp8732-ldo1";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi
index c59edf9..6853d4d 100644
--- a/arch/arm/dts/dra72-evm-common.dtsi
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -242,6 +242,38 @@
 			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
 		>;
 	};
+
+	nand_flash_x16: nand_flash_x16 {
+		/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+		 * So NAND flash requires following switch settings:
+		 * SW5.9 (GPMC_WPN) = LOW
+		 * SW5.1 (NAND_BOOTn) = HIGH */
+		pinctrl-single,pins = <
+			0x00	(PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+			0x04	(PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+			0x08	(PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+			0x0c	(PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+			0x10	(PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+			0x14	(PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+			0x18	(PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+			0x1c	(PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad7 */
+			0x20	(PIN_INPUT | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
+			0x24	(PIN_INPUT | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
+			0x28	(PIN_INPUT | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
+			0x2c	(PIN_INPUT | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
+			0x30	(PIN_INPUT | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
+			0x34	(PIN_INPUT | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
+			0x38	(PIN_INPUT | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
+			0x3c	(PIN_INPUT | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
+			0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* T1 : gpmc_cs0 */
+			0xb8	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* P2 : gpmc_cs1.gpmc_wp */
+			0xc4	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* N1 : gpmc_advn_ale */
+			0xc8	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* M5 : gpmc_oen_ren */
+			0xcc	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* M3 : gpmc_wen */
+			0xd0	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* N6 : gpmc_ben0 */
+			0xd8	(PIN_INPUT | MUX_MODE0)	/* N2 : gpmc_wait0 */
+		>;
+	};
 };
 
 &dra7_iodelay_core {
@@ -408,6 +440,11 @@
 	};
 };
 
+&i2c4 {
+	status = "okay";
+	clock-frequency = <400000>;
+};
+
 &i2c5 {
 	status = "okay";
 	clock-frequency = <400000>;
@@ -451,7 +488,9 @@
 	 * support NAND on dra72-evm. Keep it disabled. Enabling it
 	 * requires a different configuration by U-Boot.
 	 */
-	status = "disabled";
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x16>;
 	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
 	nand@0,0 {
 		/* To use NAND, DIP switch SW5 must be set like so:
@@ -587,11 +626,12 @@
 &mmc2 {
 	/* SW5-3 in ON position */
 	status = "okay";
-	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+	/*pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; FS:RAJ*/
+	pinctrl-names = "default", "hs", "ddr_1_8v";
 	pinctrl-0 = <&mmc2_pins_default>;
 	pinctrl-1 = <&mmc2_pins_hs>;
 	pinctrl-2 = <&mmc2_pins_ddr_1_8v>;
-	pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>;
+	/*pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>; FS:RAJ*/
 
 	vmmc-supply = <&evm_3v3>;
 	bus-width = <8>;
@@ -608,7 +648,7 @@
 };
 
 &qspi {
-	status = "okay";
+	status = "disabled";
 
 	spi-max-frequency = <64000000>;
 	m25p80@0 {
diff --git a/include/config_defaults.h b/include/config_defaults.h
index ad08c1d..8411bed 100644
--- a/include/config_defaults.h
+++ b/include/config_defaults.h
@@ -9,8 +9,11 @@
 #ifndef _CONFIG_DEFAULTS_H_
 #define _CONFIG_DEFAULTS_H_
 
+/* FS:RAJ */
+#define BOOT_OPT
 /* Support bootm-ing different OSes */
 #define CONFIG_BOOTM_LINUX 1
+#ifndef BOOT_OPT
 #define CONFIG_BOOTM_NETBSD 1
 #define CONFIG_BOOTM_PLAN9 1
 #define CONFIG_BOOTM_RTEMS 1
@@ -18,6 +21,7 @@
 
 #define CONFIG_GZIP 1
 #define CONFIG_ZLIB 1
+#endif
 #define CONFIG_PARTITIONS 1
 
 #endif
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 766a212..2c87310 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -12,13 +12,14 @@
  * features required by distros to support boards in a standardised and
  * consistent manner.
  */
-
+#ifndef BOOT_OPT
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
+#endif
 
 #if defined(__arm__) || defined(__aarch64__)
 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
@@ -44,17 +45,18 @@
 #ifdef CONFIG_ARM64
 #define CONFIG_CMD_BOOTI
 #endif
+#define CONFIG_BOOTDELAY     0
+#define CONFIG_MENU
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#ifndef BOOT_OPT
 #define CONFIG_CMD_PXE
-
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_BOOTDELAY     2
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_MENU
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
 #define CONFIG_ISO_PARTITION
 #define CONFIG_SUPPORT_RAW_INITRD
+#endif
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 
 #endif	/* _CONFIG_CMD_DISTRO_DEFAULTS_H */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 35d373e..db0c9d8 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -12,8 +12,6 @@
 #ifndef __CONFIG_DRA7XX_EVM_H
 #define __CONFIG_DRA7XX_EVM_H
 
-#include <environment/ti/dfu.h>
-
 #define CONFIG_DRA7XX
 #define CONFIG_BOARD_EARLY_INIT_F
 
@@ -30,7 +28,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
 #define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_ENV_OFFSET		0x260000
+#define CONFIG_ENV_OFFSET		0x140000
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #endif
@@ -47,6 +45,7 @@
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
 
+
 #ifndef CONFIG_SPL_BUILD
 /* Define the default GPT table for eMMC */
 #define PARTS_DEFAULT \
@@ -56,17 +55,16 @@
 	/* Android partitions */ \
 	"partitions_android=" \
 	"uuid_disk=${uuid_gpt_disk};" \
-	"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
-	"name=bootloader,size=2304K,uuid=${uuid_gpt_bootloader};" \
-	"name=environment,size=256K,uuid=${uuid_gpt_environment};" \
+	"name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \
+	"name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
+	"name=environment,size=128K,uuid=${uuid_gpt_environment};" \
 	"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
 	"name=reserved,size=384K,uuid=${uuid_gpt_reserved};" \
 	"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
 	"name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
-	"name=recovery,size=30M,uuid=${uuid_gpt_recovery};" \
+	"name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
 	"name=boot,size=10M,uuid=${uuid_gpt_boot};" \
 	"name=system,size=768M,uuid=${uuid_gpt_system};" \
-	"name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
 	"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
 	"name=ipu1,size=8M,uuid=${uuid_gpt_ipu1};" \
 	"name=ipu2,size=8M,uuid=${uuid_gpt_ipu2};" \
@@ -74,6 +72,50 @@
 	"name=dsp2,size=8M,uuid=${uuid_gpt_dsp2};" \
 	"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
 
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x400;" \
+	"spl-os-args.raw raw 0x80 0x80;" \
+	"spl-os-image.raw raw 0x900 0x2000;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+	"dfu_alt_info_emmc=" \
+	"rawemmc raw 0 3751936;" \
+	"boot part 1 1;" \
+	"rootfs part 1 2;" \
+	"MLO fat 1 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x400;" \
+	"spl-os-args.raw raw 0x80 0x80;" \
+	"spl-os-image.raw raw 0x900 0x2000;" \
+	"spl-os-args fat 1 1;" \
+	"spl-os-image fat 1 1;" \
+	"u-boot.img fat 1 1;" \
+	"uEnv.txt fat 1 1\0"
+
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0x4000000;" \
+	"fdt ram 0x80f80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFU_ALT_INFO_QSPI \
+	"dfu_alt_info_qspi=" \
+	"MLO raw 0x0 0x040000;" \
+	"u-boot.img raw 0x040000 0x0100000;" \
+	"u-boot-spl-os raw 0x140000 0x080000;" \
+	"u-boot-env raw 0x1C0000 0x010000;" \
+	"u-boot-env.backup raw 0x1D0000 0x010000;" \
+	"kernel raw 0x1E0000 0x800000\0"
+
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \
 	DFU_ALT_INFO_MMC \
@@ -92,21 +134,19 @@
 
 #define CONFIG_ANDROID_BOOT_IMAGE
 
+#define CONFIG_BOOTARGS_BOARD		"console=ttyS0,115200 " \
+					"androidboot.console=ttyS0 " \
+					"androidboot.hardware=jacinto6evmboard"
+
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_CMD_BOOTD
 #ifdef CONFIG_SPL_DFU_SUPPORT
 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_HASH_SUPPORT
-
-#ifdef CONFIG_SPL_LOAD_FIT
-#define DFUARGS \
-	"dfu_bufsiz=0x10000\0" \
-	DFU_ALT_INFO_RAM
-#else
 #define DFU_ALT_INFO_RAM \
 	"dfu_alt_info_ram=" \
-	"kernel ram 0x807fffc0 0x4000000;" \
+	"kernel ram 0x80200000 0x4000000;" \
 	"fdt ram 0x80f80000 0x80000;" \
 	"ramdisk ram 0x81000000 0x4000000\0"
 #define DFUARGS \
@@ -114,7 +154,6 @@
 	DFU_ALT_INFO_RAM
 #endif
 #endif
-#endif
 
 #include <configs/ti_omap5_common.h>
 
@@ -166,6 +205,8 @@
 /* In SPL, use the environment and discard MMC support for space. */
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_SPL_MMC_SUPPORT
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE             (256 << 10) /* 256 KiB */
 #endif
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -198,8 +239,6 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_OMAP_USB2PHY2_HOST
 
-#define CONFIG_USB_FUNCTION_MASS_STORAGE
-
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
@@ -220,6 +259,8 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 
+
+#define CONFIG_NAND			1
 /* NAND support */
 #ifdef CONFIG_NAND
 /* NAND: device related configs */
@@ -232,9 +273,14 @@
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 /* NAND: driver related configs */
 #define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_BASE            0x8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD
+#define CONFIG_CMD_MTDPARTS
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
 #define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
@@ -316,8 +362,6 @@
 #define CONFIG_PCF8575_GPIO
 #endif
 
-#define CONFIG_LZO
-
 /* JAMR3 board pin mux */
 #define CONFIG_DRA7XX_JAMR3
 
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 7d5255c..a748b24 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -64,32 +64,11 @@
 	"args_mmc=run finduuid;setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=PARTUUID=${uuid} rw " \
+		"lpj=61475 " \
 		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"bootenvfile=uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
 	"loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
 	"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
 	"envboot=mmc dev ${mmcdev}; " \
-		"if mmc rescan; then " \
-			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootscript; then " \
-				"run bootscript;" \
-			"else " \
-				"if run loadbootenv; then " \
-					"echo Loaded env from ${bootenvfile};" \
-					"run importbootenv;" \
-				"fi;" \
-				"if test -n $uenvcmd; then " \
-					"echo Running uenvcmd ...;" \
-					"run uenvcmd;" \
-				"fi;" \
-			"fi;" \
-		"fi;\0" \
 	"mmcloados=run args_mmc; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
@@ -110,6 +89,16 @@
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
 			"if run loadimage; then " \
+					"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+/* BOOT_OPT */
+/*	"mmcboot=mmc dev ${mmcdev}; " \
+		"setenv devnum ${mmcdev}; " \
+		"setenv devtype mmc; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadimage; then " \
 				"if test ${boot_fit} -eq 1; then " \
 					"run loadfit; " \
 				"else " \
@@ -117,6 +106,7 @@
 				"fi;" \
 			"fi;" \
 		"fi;\0" \
+*/
 
 #define DEFAULT_FIT_TI_ARGS \
 	"boot_fit=0\0" \
@@ -170,8 +160,10 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 
+#ifndef BOOT_OPT
 /* McSPI IP block */
 #define CONFIG_SPI
+#endif
 
 /* GPIO block */
 
@@ -195,9 +187,12 @@
 #define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
 
 /* As stated above, the following choices are optional. */
+/* BOOT_OPT */
+/*
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
+*/
 #define CONFIG_VERSION_VARIABLE
 
 /* We set the max number of command args high to avoid HUSH bugs. */
@@ -252,17 +247,20 @@
 #define CONFIG_SPL_OS_BOOT
 #endif
 
+/* BOOT_OPT */
+#undef CONFIG_SPL_OS_BOOT
+
 /*
  * Place the image at the start of the ROM defined image space (per
  * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
- * downloaded image area minus 1KiB for scratch space.  We initalize DRAM as
- * soon as we can so that we can place stack, malloc and BSS there.  We load
- * U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict
- * with older SPLs).  We have our BSS be placed 2MiB after this, to allow for
- * the default Linux kernel address of 0x80008000 to work with most sized
- * kernels, in the Falcon Mode case.  We have the SPL malloc pool at the end
- * of the BSS area.  We suggest that the stack be placed at 32MiB after the
- * start of DRAM to allow room for all of the above (handled in Kconfig).
+ * downloaded image area.  We initalize DRAM as soon as we can so that
+ * we can place stack, malloc and BSS there.  We load U-Boot itself into
+ * memory at 0x80800000 for legacy reasons (to not conflict with older
+ * SPLs).  We have our BSS be placed 2MiB after this, to allow for the
+ * default Linux kernel address of 0x80008000 to work with most sized
+ * kernels, in the Falcon Mode case.  We have the SPL malloc pool at the
+ * end of the BSS area.  We suggest that the stack be placed at 32MiB after
+ * the start of DRAM to allow room for all of the above (handled in Kconfig).
  */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0x80800000
@@ -276,14 +274,10 @@
 					 CONFIG_SPL_BSS_MAX_SIZE)
 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
 #endif
-#ifndef CONFIG_SPL_MAX_SIZE
-#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
-					 CONFIG_SPL_TEXT_BASE)
-#endif
 
 /* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300	/* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x1000	/* 2048 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200	/* address 0x40000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300	/* 384 KB */
 
 /* FAT sd card locations. */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
@@ -292,13 +286,12 @@
 #ifdef CONFIG_SPL_OS_BOOT
 /* FAT */
 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"single-stage-boot.dtb"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
 
 /* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x1700  /* address 0x2E0000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x1500  /* address 0x2A0000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x200   /* 256KiB */
-
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
 
 /* spl export command */
 #define CONFIG_CMD_SPL
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index 7548170..de91789 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -24,8 +24,10 @@
 /* MMC/SD IP block */
 #define CONFIG_OMAP_HSMMC
 
+#ifndef BOOT_OPT
 /* SPI IP Block */
 #define CONFIG_OMAP3_SPI
+#endif
 
 /* GPIO block */
 #define CONFIG_OMAP_GPIO
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index b68e47a..ee4df51 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -63,32 +63,80 @@
 #define DFUARGS
 #endif
 
-#ifndef CONFIG_EXTRA_BOARD_ENV_SETTINGS
-#define CONFIG_EXTRA_BOARD_ENV_SETTINGS
+#ifndef BOOT_OPT
+#define NANDARGS \
+        "mtdids=" MTDIDS_DEFAULT "\0" \
+        "mtdparts=" MTDPARTS_DEFAULT "\0" \
+        "nandargs=setenv bootargs console=${console}" \
+                "${optargs}" \
+                "root=${nandroot}" \
+                "rootfstype=${nandrootfstype}\0" \
+        "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
+        "nandrootfstype=ubifs rootwait=1\0" \
+        "nandboot=echo Booting from nand ...;" \
+                "run bootargs;" \
+        "nand read ${fdtaddr} NAND.u-boot-spl-os;" \
+        "nand read ${loadaddr} NAND.kernel;" \
+        "bootz ${loadaddr} - ${fdtaddr}\0"
+#define NANDBOOT        "run nandboot;"
 #endif
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
-	DEFAULT_FIT_TI_ARGS \
+	/* DEFAULT_FIT_TI_ARGS \  BOOT_OPT */ \
 	"console=" CONSOLEDEV ",115200n8\0" \
-	"fdtfile=undefined\0" \
+	"fdtfile=dra72-evm-infoadas.dtb\0" \
 	"reboot_image=boot\0" \
 	"boot_os=0\0" \
 	"bootpart=0:2\0" \
 	"bootdir=/boot\0" \
 	"bootfile=zImage\0" \
-	"usbtty=cdc_acm\0" \
+	/* "usbtty=cdc_acm\0" \  BOOT_OPT */ \
 	"vram=16M\0" \
 	"partitions=" PARTS_DEFAULT "\0" \
 	"optargs=\0" \
-	"dofastboot=0\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
+	/* "dofastboot=0\0" \  BOOT_OPT */ \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"emmcboot_count=0\0" \
+	"max_emmcboot_count=3\0" \
+	"emmcboot_os=0\0" \
+	"emmcloados_0=" \
+		     "setenv bootpart 1:2; " \
+		     "setexpr emmcboot_count ${emmcboot_count} + 1; " \
+		     "saveenv; " \
+		     "run args_mmc; " \
+	             "if mmc rescan; then " \
+	              	  "if run loadimage; then " \
+	              	          "if run loadfdt; then " \
+	              	                  "bootz ${loadaddr} - ${fdtaddr}; " \
+	              	          "else " \
+	              	                  "echo WARN: Cannot load the DT;" \
+	              	          "fi;" \
+	              	  "else " \
+	              	          "echo WARN: Cannot load the zimage;" \
+	              	  "fi;" \
+	              "fi;\0" \
+	"emmcloados_1=" \
+   	             "setenv bootpart 1:3; " \
+		     "setexpr emmcboot_count ${emmcboot_count} + 1; " \
+		     "saveenv; " \
+		     "run args_mmc; " \
+   	             "if mmc rescan; then " \
+   	             	"if run loadimage; then " \
+   	                	"if run loadfdt; then " \
+   	                		"bootz ${loadaddr} - ${fdtaddr}; " \
+   	                        "else " \
+   	                        	"echo WARN: Cannot load the DT;" \
+			        "fi;" \
+		        "else " \
+		        	"echo WARN: Cannot load the zimage;" \
+		        "fi;" \
+		     "fi;\0" \
 	"mmcboot=" \
+		"setenv bootpart 0:2; " \
+		"saveenv; " \
 		"if mmc dev ${mmcdev}; then " \
 			"setenv devtype mmc; " \
 			"if mmc rescan; then " \
@@ -101,7 +149,31 @@
 				"fi; " \
 			"fi; " \
 		"fi;\0" \
-	"emmc_android_boot=" \
+        "emmcboot=" \
+		"setenv mmcdev 1;" \
+		"mmc dev ${mmcdev}; " \
+        	"setenv devtype mmc; " \
+                "setenv devnum ${mmcdev}; " \
+                "if test ${emmcboot_count} -ge ${max_emmcboot_count}; then " \
+			"setenv emmcboot_count 0; saveenv; " \
+                        "if test ${emmcboot_os} -eq 0; then " \
+                                "echo Booting from image 1...;" \
+                                "run emmcloados_1;" \
+                        "else " \
+                                "echo Booting from image 0...;" \
+                                "run emmcloados_0;" \
+                        "fi;" \
+                "elif test ${emmcboot_os} -eq 0; then " \
+                        "echo Booting from image 0...;" \
+                        "run emmcloados_0;" \
+                "elif test ${emmcboot_os} -eq 1; then " \
+                        "echo Booting from image 1...;" \
+                        "run emmcloados_1;" \
+                "else " \
+                        "echo  ${emmcboot_os} selection wrong; " \
+                "fi;\0" \
+/*BOOT_OPT start */ \
+	/*"emmc_android_boot=" \
 		"setenv eval_bootargs setenv bootargs $bootargs; " \
 		"run eval_bootargs; " \
 		"setenv mmcdev 1; " \
@@ -132,8 +204,6 @@
 			"setenv fdtfile dra72-evm.dtb; fi;" \
 		"if test $board_name = dra71x; then " \
 			"setenv fdtfile dra71-evm.dtb; fi;" \
-		"if test $board_name = dra76x; then " \
-			"setenv fdtfile dra76-evm.dtb; fi;" \
 		"if test $board_name = beagle_x15; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
 		"if test $board_name = beagle_x15_revb1; then " \
@@ -154,23 +224,29 @@
 			"setenv fdtfile am571x-idk-lcd-osd.dtb; fi;" \
 		"if test $board_name = am571x_idk && test $idk_lcd = osd101t2587; then " \
 			"setenv fdtfile am571x-idk-lcd-osd101t2587.dtb; fi;" \
-		"if test $board_findfdt != undefined; then " \
-			"run board_findfdt; fi;" \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	NANDARGS \
 	DFUARGS \
-	NETARGS \
-	CONFIG_EXTRA_BOARD_ENV_SETTINGS \
+	NETARGS \*/
+/* BOOT_OPT end */
 
 #ifndef CONFIG_BOOTARGS_BOARD
 #define CONFIG_BOOTARGS_BOARD
 #endif
+#ifndef BOOT_OPT
 #define CONFIG_BOOTARGS  "androidboot.serialno=${serial#} " \
 	CONFIG_BOOTARGS_BOARD
+#else
+#define CONFIG_BOOTARGS  "serialno=${serial#} " \
+	CONFIG_BOOTARGS_BOARD
+#endif
 
 #ifndef CONFIG_FASTBOOT_USB_DEV
 #define CONFIG_FASTBOOT_USB_DEV 0
 #endif
+
+#ifndef BOOT_OPT
 #define CONFIG_BOOTCOMMAND \
 	"if test ${dofastboot} -eq 1; then " \
 		"echo Boot fastboot requested, resetting dofastboot ...;" \
@@ -181,12 +257,17 @@
 	"if test ${boot_fit} -eq 1; then "	\
 		"run update_to_fit;"	\
 	"fi;"	\
-	"run findfdt; " \
-	"run envboot; " \
 	"run mmcboot;" \
+	"run emmcboot;" \
 	"run emmc_android_boot; " \
+	"run nandboot;" \
 	""
-
+#else
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot;" \
+        "run emmcboot;" \
+	""
+#endif
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
@@ -220,6 +301,12 @@
 #endif
 
 /* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
+#if defined(CONFIG_DRA7XX)
+#define CONFIG_SPL_BOOT_END		0x4037E000
+#else
+#define CONFIG_SPL_BOOT_END		0x4031E000
+#endif
+#define CONFIG_SPL_MAX_SIZE     (CONFIG_SPL_BOOT_END - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
@@ -239,12 +326,12 @@
 #undef CONFIG_DM_ETH
 #endif
 
-#define MAX_REMOTECORE_BIN_SIZE (12*0x100000)
+#define MAX_REMOTECORE_BIN_SIZE (8*0x100000)
 
 /* Define the address to which the IPU1 binary is
  * loaded from persistent storage
  */
-#define IPU1_LOAD_ADDR		(0xb0000000)
+#define IPU1_LOAD_ADDR		(0xa0fff000)
 
 /*
  * Set load address  for each core 8 MB after load
@@ -254,11 +341,6 @@
 #define DSP1_LOAD_ADDR		(IPU2_LOAD_ADDR+MAX_REMOTECORE_BIN_SIZE)
 #define DSP2_LOAD_ADDR		(DSP1_LOAD_ADDR+MAX_REMOTECORE_BIN_SIZE)
 
-#define IPU1_COMP_ADDR         (DSP2_LOAD_ADDR+MAX_REMOTECORE_BIN_SIZE)
-#define IPU2_COMP_ADDR         (IPU1_COMP_ADDR+MAX_REMOTECORE_BIN_SIZE)
-#define DSP1_COMP_ADDR         (IPU2_COMP_ADDR+MAX_REMOTECORE_BIN_SIZE)
-#define DSP2_COMP_ADDR         (DSP1_COMP_ADDR+MAX_REMOTECORE_BIN_SIZE)
-
 /* Define the GPT partition names only when they are used.
  * This prevents warnings of invalid GPT table when loading
  * binaries from FAT partition.