TMS320VC5509A: The path via HPI to access DARAM

Hi Mark,

At first, let me say that when I read your reply and reviewed my question for another time, I found out that I made a mistake in expressing my question, so I correct it now.
The path I spoke about is 

1-HPI to a MUX (HPI multiplexed with USB)
2-from that MUX to the DMA controller
3-from DMA controller to DARAM.

Then I want to clarify the matter I have in my mind a bit more. The question I have is about the connection between HPI and the peripheral bus as you can find in the image below.

Please look at the lines I have drawn blue boxes around them especially the one between HPI and the peripheral bus.
I think here we have 3 different matters:

1. Peripheral ports vs peripheral bus (you mentioned to peripheral ports of DMA while I was asking about peripheral bus) 
2. Related to item number 1 and the image above, we can conclude that there is a possible path from HPI to DARAM via peripheral bus (and not peripheral port) and DMA and if the answer is negative what is the reason of existing a connection between HPI and peripheral bus and when this could be used? I think the reason is to have access to peripherals from the host processor
3. I know that your answer comes from the image below. This part of your answer "The DMA includes a special Auxiliary port. A fifth port supports data transfers between memory and the host port interface (HPI)." In my opinion, is exactly the same as the path I showed in the first image of my question with three red boxes.

Finally, I want to refer to this part of your answer. " If you want to transfer data from the HPI to the peripheral port, you must use data memory as a temporary buffer. Transfers between the HPI and the memory ports do not use a DMA channel."

1- I didn't want to transfer data from HPI to the peripheral port.
2-What do you exactly mean by the word "data memory'? Does this indicate the RAMs?

Regards,
Hossein

Related to this part of your reply " Transfers between the HPI and the memory ports do not use a DMA channel."
I  agree with you based on the first paragraph of page 16 of SPRU587E. All of 6 channels of DMA are paths to transfer data among all of DMA ports except HPI port 

Thank you.

Hi Mark,
I've been waiting to receive any technical reply.
Thanks

Hi Hossein,

The only way to transfer data through the HPI is
1) Host processor to HPI
2) HPI to DARAM through dedicated auxiliary port that is shared with the USB module. The USB module is given the higher priority at the port.

HPI data must use the DMA through the auxiliary port, but better latency is achievable by preventing the other DMA channels from accessing the DARAM. When EHPIEXCL in DMAGCR = 0 (not exclusive), the DMA channels can use any DMA port. When EHPIEXCL = 1 (exclusive), the DMA channels cannot access the DARAM and SARAM ports; they can access only the EMIF port (for external memory) and the peripheral port. But EMIF and HPI share the same pins, and cannot both be pin muxed simultaneously (EBSR register).

The HPI is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5509A. 32K bytes = 16K words (16-bit) from DARAM word address 000060h to 004000h.

I think the arrowed line in the block diagram that connects EHPI block to the peripheral bus must be there for the EHPI General-Purpose I/O registers. Six control lines of the External Parallel Bus can also be set as general-purpose I/O when the Parallel Port Mode bit field of the External Bus Selection Register is set to Nonmultiplexed EHPI (10) or Multiplexed EHPI mode. These pins are controlled by three registers: EHPIGPIOEN, EHPIGPIODIR, and EHPIGPIODATA. HPI data cannot use this path.

I think it must be a mistake in SPRU587E when it says
"When EHPIEXCL = 1, the HPI cannot access external memory, but it can access internal RAM without interruptions from the channels." - HPI could never access anything except 16K words in DARAM.

Also Figure 7. HPI Access Configurations looks misleading - HPI could never access SARAM or external memory.

The point they are trying to make is that HPI can have exclusive access to DARAM when EHPIEXCL = 1, but then DMA cannot access any DARAM or SARAM.
Or when EHPIEXCL = 0, HPI can access DARAM but it will compete in priority with the remaining DMA channels that can also access DARAM, SARAM, and peripherals. Again, EMIF and HPI share the same pins, and cannot both be pin muxed simultaneously.

Regards,
Mark