CCS/TMS320C6655: Linker Section Ordering

Stuart Tenenbaum

Part Number: TMS320C6655
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

Hi,

I'm trying to build a SPI boot image for our C6655 custom board. The image needs to load directly into DDR3 so I have added a DDR configuration table @ 0x008FFD20 in my code. The linker obediently places this section at the proper address. The problem is that this section is not listed/output first in the .out file. Other sections which reside in DDR are being output ahead of my DDR configuration table section. Consequently, DDR is not yet configured when the C6655 RBL encounters these early sections. To be clear, all sections are located at the proper address. It is simply the order in which these sections are listed in the .out file (and eventually the .btbl file output by hex6x) that is causing the problem.

Is there a way to tell CCS (or hex6x) to output my DDR configuration table section first? I'm using CCS V8 in IDE/project mode so it automatically generates the linker command file. I believe I could get around this problem if I built from the command line, specified my own linker command file, and made sure the DDR configuration table section was listed first. But that seems like a big change this late in the development cycle.

Thanks

over 7 years ago

0 George Mock over 7 years ago

TI__Guru**** 252740 points

The linker has never had any mechanism for controlling the order in which sections appear in the .out file. There must be some other way to solve your problem. I'll ask some C6000 device experts to look at this thread.

Thanks and regards,

-George

0 Rahul Prabhu over 7 years ago

TI__Guru** 116780 points

Stuart,

Have you seen the example for SPI boot with DDR initialization that we provide herE:
processors.wiki.ti.com/.../KeystoneI_Bootloader_Resources_and_FAQ

IF you check the main.c and the linker command file, this should show how the DDR configuration table need to added to the boot image for DDR initialization. Is it possible for you to share your linker command file. what do you mean by linker command file is automatically generated by CCS. Are you using a TI RTOS project where the linker command file is generated from the platform definition. If that is the case, how are you instructing the linker to place the DDR configuration table in the location expected by ROM?

While the ROM bootloader for the device was designed to initialize DDR, there have been changes to the DDR init sequence in the USer guide and also the HW leveling hence we have observed a lot of users have choosen to use a two stage boot approach where the secondary bootloader configures the DDR instead of ROM.

Regards,
Rahul

0 Stuart Tenenbaum over 7 years ago in reply to Rahul Prabhu

Prodigy 150 points

Hi Rahul,
Yes, I am using a TI RTOS project so the linker command file is generated from the platform definition. In order to place the DDR configuration table in my code I placed a #pragma DATA_SECTION(DDRConfigTable,".emif4Cfg") ahead of my table declaration (DDRConfigTable) and then added the following lines to my CFG file:
Program.sectMap[".emif4Cfg"] = new Program.SectionSpec();
Program.sectMap[".emif4Cfg"].loadAddress = 0x008FFD20;

As I mentioned earlier, the linker dutifully outputs my DDRConfigTable at the proper address (0x008FFD20). It just doesn't output that section first, or at least ahead of all other DDR sections.

However, based on the latter comments in your reply, it sounds like I may need a SBL to perform DDR initialization so this discussion may be moot.

Thanks,
Stuart

0 Rahul Prabhu over 7 years ago in reply to Stuart Tenenbaum

TI__Guru** 116780 points

Stuart,

XDC autogenerates the linker command file based on the platform definition and then adds addition user sections defined in the application cfg file to place the DDR config section first, you may need to put all your DDR sections also in the application cfg file so that your .emif4CFg section is listed first.

The other option is to add a .cmd file to the SYSBIOS project and not define the Memory section in the linker command file but only define the SECTIONS as shown below so you define the way the sections are organized.

MEMORY
{
DDR_CFG : origin = 0x8ffd20, length = 0x180
}

SECTIONS
{
.emif4Cfg > DDR_CFG

.stack > DDR3
.msmc > DDR3
.data > DDR3
.far > DDR3
.text > DDR3
.const > DDR3
.cinit > DDR3

}

DDR section is defined in the Platform define in BIOS. One problem that you may run into is that the BIOS platform defines L2SRAM and disables L2 cache so when you try to place code using DDR_CFG as shown above, it may report overlapping sections.

the alternate way to handle this would be to create a custom RTSC platform for your C665x as described here:

http://rtsc.eclipse.org/docs-tip/Demo_of_the_RTSC_Platform_Wizard_in_CCSv4

Regards,

Rahul

0 Stuart Tenenbaum over 7 years ago in reply to Rahul Prabhu

Prodigy 150 points

In the end, I used SPIBoot as separate .out and .btbl files and combined it with my application code using BFMerge. This allowed me to specify the order and place SPIBoot (the DDR configuration table) first in the boot image.

BTW, the multitude of TI documents, application notes, white papers, and E2E posts make the Keystone C665x boot process incomprehensible. There is no single document and more importantly no single tool to unify the .out file to boot image process. Both are desperately needed. For the record, the best description of the process I found is here:
au.tono.my/.../20140117-c6657-spi-boot.html

Regards,
Stuart

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CCS/TMS320C6655: Linker Section Ordering