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AM3352: What is PAD?

Part Number: AM3352

Hi, there.

I'm new to TI processor, and now i'm using am3352.

That I saw the "PAD" for the first time is confusing me. What its meaning?

Also, excerpt in am335x arm cortex-a MPU tech ref manual page 4079(SPRUH73H–October 2011–Revised April 2013):

"The GPIO_OE register is used to enable the pins output capabilities. At reset, all the GPIO related pins are configured as input and output capabilities are disabled. This register is not used within the module, its only function is to carry the pads configuration"

I don't understand the last sentence "to carry the pads configuration".

What is pad actually?

  • Hi,

    See section 9.2.2 of the TRM. In summary, pad = pin.
  • Part Number: AM3352

    Hi, there.

    I'm reading am335x arm cortex-a8 MPU tech ref manual, and the following description to RX Active:

    The RXACTIVE bit is used to enable and disable the input buffer. This control can be used to help with
    power leakage or device isolation through the I/O. The characteristic of the signal is ultimately dictated by
    the mux mode the pad is put into.

    I've searched the related topic in this forum and found nothing.

    1. I can't put these two things "input buffer" and "help with power leakage or device isolation through the I/O" together.

    2. Also, I'm not understanding sentence "The characteristic of the signal is ultimately dictated by the mux mode the pad is put into".

    Is that signal the "signal name"?

    What is this characteristic? RXACTIVE?

    What does "dictated by the mux mode" mean?

    Thank you.

     

  • Thank you.
    Actually, I already read it.
    This section gave me a sense that pad = a group of pins. Right?
  • No, "pad" and "pin" are the same. One pad/pin can have differtent functionality, depending on the mode selected in the pad configuration register.
  • Andy Lin94 said:
    1. I can't put these two things "input buffer" and "help with power leakage or device isolation through the I/O" together.

    When the input buffer is enabled there will be a small input current leaking through the pin.

    Andy Lin94 said:
    2. Also, I'm not understanding sentence "The characteristic of the signal is ultimately dictated by the mux mode the pad is put into". Is that signal the "signal name"?

    Yes.

    Andy Lin94 said:
    What is this characteristic? RXACTIVE?

    RXACTIVE = input buffer enabled.

    Andy Lin94 said:
    What does "dictated by the mux mode" mean?

    Mux mode = pin functional mode.

  • Thanks, I will remember that pad and pin are the same
  • In summary:

    For example: The RXACTIVE is disabled, the power leakage is 0.1mwatt. If the RXACTIVE have enabled, the power leakage would be less than 0.1mwatt. Right?

    Since it looks like there are no disadvantages. Why don't MPU default it as enabled? What are disadvantages?
    I'm afraid of asking too detail. Do you mind give me related keywords as alternative for me to google it?

    About the second question, I have to apologize that maybe I'm not pointing well my question out.
    My question is: How mux mode can dictate this characteristic? By what means? Muxmode only control pin's mode, and this characteristic is controlled only by RXACTIVE bit.

    Given that this is my first time to visit this forum, do I put the different topics into one thread? Thank you.

  • Device isolation is mainly needed when the processor is put in low-power mode, when it's important to reduce power consumption as much as possible. Power leakages must be avoided in this case.

    The signal characteristic is definitely dictated by the mode in which the pin is placed. A given pin can be pinmuxed to SPI, Ethernet, UART, GPIO, etc... and all these signals have different characteristics.
  • Thank you very much....I fully understand the second question right now.
    I'm not a English native speaker, so sometimes I interpret sentence meaning into wrong way.

    I'm still not figuring out question 1, also, I've edited my previous comment.

    I want to confirm that:
    1.1. No matter RX Active is enabled or disabled, there is always a power leakage through the I/O pin.
    1.2. If RX Active is enabled, power leakage is getting lower.
    1.3. lower power leakage = lower power consumption.

    or

    2.1 If RX Active is disabled, there will be power leakages.
    2.2 If RX Active is enabled, there will be no power leakages.
    2.3 If RX Active is enabled, device isolation is improved.

    Which group is correct?

    Thank you.
  • 1.1. Correct.
    1.2. If RX Active is enabled, power leakage is HIGHER.
    1.3. Correct.

    2.1. Wrong.
    2.2. Wrong.
    2.3. Wrong.
  • Thank you.

    Given that power leakage will be higher as well as device isolation will be dropped when RX Active is enabled. What situations are suited for enabling RX Active?
  • When the I/O pin is an input. Also there are special requirement for clock signals on serial interfaces, such as McSPI, I2C, MMC - they must have RX Active enabled on the clock signals even if they are output, because these are used for data input retiming purposes at pin level.