Linux/AM3352: Enabling SSC

Tony,

LCD PLL and DISP (Display) PLL is the same. And AM335x device support SSC on MPU PLL and DISP PLL:

Additional timing margins are required when enabling Spread Spectrum Clocking (SSC). This prevents SSC from being enabled on any of the PLLs that source clocks to peripheral interfaces. We have determined SSC can be enabled on the MPU and Display PLL's since they only source clocks to dedicated circuits and interfaces that do not require low jitter clocks. The other PLLs will effect peripheral timing, so SSC should not be enabled on any PLLs other than MPU and Display.


See also below e2e threads:

e2e.ti.com/.../454523
e2e.ti.com/.../198104

I think the AM335x TRM needs an update for this NOTE. I will submit TRM update request. I will propose the below update:

NOTE: Spread spectrum clock is only supported for the DISP/LCD and MPU PLLs on this device. Spread spectrum clocking is not supported for DDR, PER, and CORE PLLs. When enabling SSC on MPU PLL, ensure the maximum MPU frequency remains below the maximum rated frequency for the chosen OPP (see the device-specific Data Manual for more details).

Regards,
Pavel

Pavel,

#1. Is u-boot-2018.01/board/siemens/rut/board.c verified by TI? Or is it implemented by Simens and support by TI?

#2. How to use it? replace the board.c under arch/arm/mach-omap2/am33xx?  or just add the this file to makefile to build for own board?

#3. in TRM, the reserved register address is defined with name, why name it reserved in the UBOOT code?

#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
unsigned int wkctrlclkctrl; /* offset 0x04 */
unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
unsigned int timer0clkctrl; /* offset 0x10 */
unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
unsigned int sscdeltamstepdllmpu; /* off 0x24 */
unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
unsigned int clkseldpllmpu; /* offset 0x2c */
unsigned int resv4[1];
unsigned int idlestdpllddr; /* offset 0x34 */
unsigned int resv5[2];
unsigned int clkseldpllddr; /* offset 0x40 */
unsigned int resv6[4];
unsigned int clkseldplldisp; /* offset 0x54 */
unsigned int resv7[1];
unsigned int idlestdpllcore; /* offset 0x5c */
unsigned int resv8[2];
unsigned int clkseldpllcore; /* offset 0x68 */
unsigned int resv9[1];
unsigned int idlestdpllper; /* offset 0x70 */
unsigned int resv10[2];
unsigned int clkdcoldodpllper; /* offset 0x7c */
unsigned int divm4dpllcore; /* offset 0x80 */
unsigned int divm5dpllcore; /* offset 0x84 */
unsigned int clkmoddpllmpu; /* offset 0x88 */
unsigned int clkmoddpllper; /* offset 0x8c */
unsigned int clkmoddpllcore; /* offset 0x90 */
unsigned int clkmoddpllddr; /* offset 0x94 */
unsigned int clkmoddplldisp; /* offset 0x98 */
unsigned int clkseldpllper; /* offset 0x9c */
unsigned int divm2dpllddr; /* offset 0xA0 */
unsigned int divm2dplldisp; /* offset 0xA4 */
unsigned int divm2dpllmpu; /* offset 0xA8 */
unsigned int divm2dpllper; /* offset 0xAC */
unsigned int resv11[1];
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
unsigned int wkup_adctscctrl; /* offset 0xBC */
unsigned int resv12;
unsigned int timer1clkctrl; /* offset 0xC4 */
unsigned int resv13[4];
unsigned int divm6dpllcore; /* offset 0xD8 */
};

Tony,

Tony Tang said:

#1. Is u-boot-2018.01/board/siemens/rut/board.c verified by TI?

I am not aware, I can not comment.

Tony Tang said:

Or is it implemented by Simens

I think yes

Tony Tang said:

and support by TI?

I think no

Tony Tang said:

#2. How to use it? replace the board.c under arch/arm/mach-omap2/am33xx?  or just add the this file to makefile to build for own board?

I would recommend to update u-boot/arch/arm/mach-omap2/am33xx/clock_am33xx.c and u-boot/board/ti/am335x/board.c files with DPLL_DISP setup, you can use RUT board.c as reference and also below file:

Tony Tang said:

#3. in TRM, the reserved register address is defined with name, why name it reserved in the UBOOT code?

I am not aware of the reason. I can state that we have these registers fully defined in linux kernel:

linux-kernel/arch/arm/mach-omap2/cm33xx.h

#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET                      0x0044
#define AM33XX_CM_AUTOIDLE_DPLL_DISP                                        AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET                             0x0048
#define AM33XX_CM_IDLEST_DPLL_DISP                                              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET      0x004c
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET    0x0050
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET                         0x0054
#define AM33XX_CM_CLKSEL_DPLL_DISP                                          AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)

Regards,
Pavel