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TMS320VC5507: Any other SRAM other than IDT71V016S25 and TC55V1664FT-12 suitable for TMS320VC5507?

Hossein Forouzani
Genius 3030 points
Part Number: TMS320VC5507

Hello,

We know that EMIF (External Memory Interface) provides a glueless interface to synchronous and asynchronous external memories and in some projects, using flash memories and/or SRAMs is necessary. There are different SRAMs produced by different semiconductor companies, such as IDT71V016S25 from IDT and TC55V1664FT-12 from Toshiba.
Is there any other SRAMs suggested suitable for TMS320VC5507/09/10 with EMIF considerations?

I don't want only a part number, but I want to find a new suggestion which could be matched with C55x's EMIF unit.

Regards,
Hossein

  • 0
    TI__Mastermind 30140 points
    Hi Hossein,

    I usually open the datasheet of the potential memory and verify that its timings and waveforms are compatible with the timings and waveforms of the processor datasheet. Refer to 5.7.1 Asynchronous Memory Timings and
    5.7.2 Synchronous DRAM (SDRAM) Timings in the 5507 datasheet.

    Do you plan to boot from this memory? There may be special considerations for the bootloader. Refer to www.ti.com/.../spra840

    The 5507 supports a total on-chip memory of 192K bytes (64K 16-bit words of RAM and 32K 16-bit words of ROM).
    You may require SDRAM in addition to nonvolatile memory.
    The 5507 supports access upto 2MB Asynch SRAM - 8 or 16 bit and 16MB SDRAM.
    So unless there is a price break, there is little reason to use larger memories... Assuming the smaller memories are available from distributers.

    Make sure not to get a memory that requires a protocol that is not supported by the 5507 - like DDR memory or NAND.

    Does this help?

    Regards,
    Mark
  • 0 in reply to Mark M
    Genius 3030 points

    Hi Mark,
    Thank you for your reply.

    Mark Mckeown said:

    I usually open the datasheet of the potential memory and verify that its timings and waveforms are compatible with the timings and waveforms of the processor datasheet. Refer to 5.7.1 Asynchronous Memory Timings and
    5.7.2 Synchronous DRAM (SDRAM) Timings in the 5507 datasheet.

    Yes, that's completely true and I agree with you. The main reason made me ask this question is to find other engineers' experience. Maybe some other people have had worked with SRAMs other than those I said and the results were satisfying so that we could exchange our code. You know, I've worked with some of C5000 TI's DSPs from some years ago and sometimes I found some mistakes in the datasheets and reported them via E2E forums. One of the important part which made some troubles for me was the schematic figures in the datasheet of TMS320VC5507 illustrating the way of connecting the device to synchronous and asynchronous memories for different packages of this device, and after reporting the problem, they accept to modify the next version of the datasheet.

    Mark Mckeown said:

    Do you plan to boot from this memory? There may be special considerations for the bootloader. Refer to www.ti.com/.../spra840

    Thanks, I have read this document.

    Mark Mckeown said:

    Make sure not to get a memory that requires a protocol that is not supported by the 5507 - like DDR memory or NAND.

    Yes, that's obviously true.

    Last but not the least,

    I feel the answers on e2e.ti.com in the past were more in detail and people were more active here. I don't know how much this idea is true.

    Regards,
    Hossein