Hi all,
I am working on DM6437. I intend to use DMA for transferring data
from external Memory (DDR2) to internal memory (L1DSRAM).
DDR2 runs at 162Mhz and configured to have bus-width of 32bits.
DMAN3 and ACPY3 interface is used with QDMA Channels to accomplish
the above mentioned task. I am exploring ways to configure the
transfers so as to achieve maximum possible throughput.
The minimum transfer size required by my application is 672bytes and
i need four such transfers (as the Source Addresses are different).
Therefore my total transfer size is 2688 bytes.
I am using Time stamp counter to profile the DMA transfer time.
Scenario #1
Single logical channel with four linked transfers are used.
So for every transfer, DMA overhead is one ACPY3_start() and one ACPY3_wait()
functions. I could see that the about 3800 cycles were consumed to
transfer 2688 bytes.
Scenario #2
In this case, Four logical channels each with single transfers were used.So for
every transfer, DMA overhead is four ACPY3_start() and four ACPY3_wait()
functions. I found that only about 2800 cycles were consumed in transferring
2688 bytes. Cycles mentioned here was profiled from the end of first ACPY3_start()
function .Please note that all the logical channels have same priority
level.
Could somebody explain me as to why the transfer time in scenario #2 is less
than that in scenario #1 for the same transfer size?
DM643x devices have three TCs. Is it because multiple channels would get
distributed among TCs and transfers possibly happening in parallel? However
this seems unlikely as all the TCs have to access the same DDR2 resulting
in port conflict. Please do correct me if my understanding is wrong.
Another question related to TC. Each of the TCs do have different configuration
w.r.t FIFO size, bus-width, Burst size...How does the user control routing of
transfer request to the desired TC? Is it by assigning priority levels to
logical channels.
Regards,
John
