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TMS320C6655: Errata Advisory 3 workaround 3 Incremental leveling after partial implementation

Adam Dupuis
Prodigy 80 points

Part Number: TMS320C6655

Hello,

 

We are now trying to implement the read eye incremental  leveling and we have a long list of questions.

  1. Is Workaround 3 implemented after workaround 1 or does it replace workaround1?

  2. Errata Advisory 3 workaround 3  only shows config_reg_60 = 0 but they don’t indicate what the other registers should be, 52 to 55.
    1. Do they actually mean that reg 52,53,54,55 and 60 should have the lower 8 bits set to 0 with bit 9 set to 1 and the default 0xD000 applied? I.e should the value be 0xD200 for the 5 registers?
    2. Or do they want 52,53,54 and 55 set to 0x0200 with 60 set to 0x0?

  3. Please clarify the sprabl2e incremental leveling examples. Page 16. Examples 25 and 26. user guides don't provide any details on some of the registers.

    1. Register descriptions for RDWR_LVL_RMP_WIN and RDWR_LVL_RMP_CTRL don’t explain what the values in the examples are doing.
        1. RDWR_LVL_RMP_WIN = 0x00000502  why?
        2. RDWR_LVL_RMP_CTRL = 0x80030300, I know the 8 is the enable but why the value 0x30300?

    2. RDWR_LVL_CTRL is set to 0x7f090900
        1. Bit 31 enables full leveling, how is the incremental enabled? Is it enabled in RDWR_LVL_CTRL through a non zero value in bits, 23-16,15-8 and 7-0?

        2. Bits 30-24 set the pre-scalar of refresh periods, what exactly is this doing? Is this at multiplier of some sort against the RD, GATE and Write incremental values?

        3. RDLVLINC_INT, RDLVLGATEINC_INT and WRLVLINC_INT look to be the enables for the incremental leveling but also include the number of RDWRLVLINC_PRE intervals…

        4. PRE_SCALAR x N = time between incremental values. 7.8 us x N intervals, example uses 0x09 = 78 us per incremental value? 

    3. How do we know when an incremental leveling has been achieved? Do we rely on a time limit for the 64 values to occur? 64 * 78 us = 4.99 ms....

                                                               i.      Also I assume that with bits 23 down to 0 being set the incremental leveling's will continue until set to 0 hence example 26.

  1. I assume if partial auto leveling is implanted then there is no need to implement the incremental gate leveling seeing as it is only the RD_DATA_EYE training that is broken.
  1. Or is TI recommending training the GATE and DATA EYE?
  2. I assume we don’t bother with incremental write leveling because it too is broken and already leveled through partial auto leveling?

 

Cheers,

 

Adam

  • 0
    TI__Mastermind 46460 points

    Adam,

    The recommended DDR3 configuration method is documented in the KeyStone I DDR3 Initialization Application Report.  The full commissioning process is documented on the wiki page  .

    This does not use incremental leveling.  The incremental leveling feature was added to the PHY to support a dynamic CVDD voltage control mechanism.  Since we decommissioned that voltage control mechanism as it was not needed for power reduction, there is no need for use of the incremental leveling features.  That is why they are not discussed in the Initialization document and not contained in the example code provided in ProcSDK.  DDR3 PHY operation is known robust as implemented in the ProcSDK.  There is limited software support for these unsupported features.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 80 points
    Hi Tom,

    thanks for the update, does this mean that workaround 1 is the only options we should be using? Workaround 3 makes it sound like it will fix the RD_DATA EYE training issue?

    cheers,

    Adam
  • 0 in reply to Adam Dupuis
    TI__Mastermind 46460 points

    Adam,

    Yes, Partial Automatic Leveling which is discussed in Workaround 1 is the solution that is fully productized in the sample software.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 80 points
    Thanks Tom,

    The part I don't understand is that the partial leveling uses a default value of 0x34 for the lower 8 bits of the Read eye... and no leveling is done to adjust this. Workaround 3 seems to imply that it fixes this limitation by allowing incremental read eye training...

    1. Have i understood this correctly?
    2. Why is workaround 3 not recommended?
    3. couldn't the default value of 0x34 put the eye training on the edge and eventually fail or temperature and rail variations?
  • 0 in reply to Adam Dupuis
    Prodigy 80 points
    PS i understand that work around 3 was mainly for the CVDD feature you mentioned but can it be used to fix the read eye training issue?
  • 0 in reply to Adam Dupuis
    TI__Mastermind 46460 points

    Adam,

    Timing analysis validated that using the static value of 0x34 met all margin requirements for the qualified silicon and the range of supported operating conditions.  There is no need to implement workaround 3.  Partial Automatic Leveling is the solution implemented by almost all customers with boards in production.  We had customers provision boards with the alternative workarounds but there was additional effort needed.  Therefore, since Partial Automatic Leveling meets all long term requirements and has been proven robust through timing analysis and many many customer designs as reflected in the sample code, we recommend that customers use this implementation.

    Tom