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Discrepancy in DSK5510 and 5510 datasheet

Aditi Akula
Expert 1440 points

Hi,

I am working on a C5510A (silicon rev 2.2) DSP, and have some questions with regard to the pull-ups and pull-downs on

some DSP pins in my design as compared to the DSK5510 (with C5510A DSP).

                                                     In my design :                                                                               DSK5510

HBE0/HBE1  ---                        100 ohm pull-downs                                                      Have 10k pull-ups on both

RST_MODE  ---                     100 ohm pull-down                                                                          10k Pull-up

HOLD           ---                      nothing, goes to a test point                                                           10k Pull-up

HRDY           ---                      directly to the FPGA (host)                                                               10k Pull-up

HCNTL0      ---                      directly to the FPGA (host)                                                               10k pull-up

 

The datasheet says that HBE0/HBE1 must be pulled low. And any external state on RST_MODE will have no effect.

Why does the DSK board have pull-ups on HBE1/HBE2/RST_MODE?

Are my connections correct ? Or do I need to have pull-ups like the DSK board on some of the DSP pins?

If so, on which ones?

Thanks

Aditi.

 

 

  • 0
    TI__Expert 8065 points

    Aditi,

    I do not know why the C5510DSK has pull-ups for the pins. It was designed long ago and I can't find person who designed the board. However, I would go by datasheet. Datasheet has the correct information. 

    According to the datasheet, HEB0/1 pin can be pulled down externally or by the internal pulldown circuit controlled by the HPE bit in the SYSR register.

    For RST_MODE pin, I would put a pull-up resister rather than a pull-down resistor. Even if it does not affect on device operation, pull-up is safer, I think. 

     

    Best Regards,

    Peter Chung

     

  • 0 in reply to Peter Chung
    Genius 3420 points

    Peter-

    Do you know if there is a power sequence or ramp-up requirement for the 5510?  I saw this TI Wiki that mentions theC550A/07/06/03, but not 5510:

      http://processors.wiki.ti.com/index.php?title=55x_FAQ

    Also the data sheet and errata do not mention.  But, the 5510 came out in a time period when some TI DSPs did require specific Vcc sequencing and/or power-on ramp shape, so I thought I'd ask.

    Thanks.

    -Jeff

  • 0 in reply to Jeff Brower73
    TI__Genius 11605 points

    Jeff: Same as C5509a and its derivatives such as C5507, 06, and 03, current rev of C5510 does not require power sequencing.

     

    Regards.

    Naser

  • 0 in reply to Naser S.
    Genius 3420 points

    Naser-

    Thanks.  Here is our power-on sequence:

      http://www.signalogic.com/images/Signalogic_C5510_power_on_sequence.jpg

    Can you confirm this looks Ok?

    Also, here is a comparison of our JTAG TCK signal with the DSK 5510:

      http://www.signalogic.com/images/Signalogic_C5510_JTAG_TCK_signal.jpg

      http://www.signalogic.com/images/DSK5510_TCK_signal.jpg

    Ours is a bit slower, maybe 1 nsec more rise-time and fall-time.  Can you confirm this is Ok?  Thanks again.

    -Jeff

     

  • 0 in reply to Jeff Brower73
    TI__Genius 11605 points

    Jeff:  I did reply to your post last Wed 11/24/10, but it looked as it if did not get updated to the post. Here is it again:

    Jeff:

    This looks ok. For C5510, there is no specific sequence of startup of the power supplies, but it is recommended that these

    Supplies power up in about the same time period. If one supply is powered up a significant time (>1 second) before the other,

    then an error is likely to occur.

     

    System-level concerns such as bus contention may require supply sequencing to be implemented. In this case,

    the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers.

     I would not use the C5510 DSK as a full reference design and compare with it. When the DSK was designed some long time ago, they added some diodes

    to compensate for some old power supplies that had poor regulation under light load at that time and to insure that core and I/O track each others.

    Some additional hints for you are:  You want the DSP rest to remain low well after both supplies are at 90% and to keep reset low long enough

    after power at 90% to get PLL stabilize. Otherwise I had seen random results and issues.

     

    Regards,

    Naser

     

     

     

  • 0 in reply to Naser S.
    Genius 3420 points

    Nasr-

    This issue is resolved, see this e2e thread:

      http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/109/p/78037/287057.aspx#287057

    Thanks very much for your help.

    -Jeff