RTOS/AM5728: Declare Memory Block in DDR

soonisys

Prodigy 250 points

Part Number: AM5728

Tool/software: TI-RTOS

I'm using idkAm5728 board and ti-rtos.

I'd like to know what I should do to declare memory block on specific address.

This memory block will be used as shared data memory.

The main application and host by pci-e will access this memory block.

https://e2e.ti.com/support/processors/f/791/t/737102

I've got answer how to declare memory block in SBL.

But, I need more information how to declare memory block in TI RTOS project.

So, This is what I need and what I know.

============ Information and what I know =============

#1. My application is based in TI-RTOS ccs project.

#2. I use idkAM5728 board.

#3. I see I have linker.cmd in project/debug/configPkg/linker.cmd

#4. I see I have app.cfg in project and there is 'Memory section configuration' in app.cfg

i.e Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";

i.e MMU configure

=========== Questions and what I need ===============

Q1. Should I declare the memory block in linker.cmd only? or both linker.cmd and app.cfg?

Q2. I'd like to declare memory block on 0x0x88000000 with 0x1000000 length. So, What should I add or edit in linker.cmd or app.cfg?

Q3. The windows pc will access this memory by pci-e(edma). So, I think I should disable cache for this memory block. Then, what should I do to disable it? or is there better way?

Q4. It looks like I have to do/config something with MMU in app.cfg for specific memory block. What should I do about MMU for this memory block?

Because I saw app.cfg in some example has this line :: Mmu.setSecondLevelDescMeta(0xXXX, 0xXXX, attrs);

Q5. I think 'spin lock' function can protect the memory when my app and host try to access at same time. Is it right? and how to enable this function for my memory block?

I'm a very newbie about am5728 and TI-RTOS....please help me guys...

And sorry for my terrible english...Thanks

over 7 years ago

0 Rahul Prabhu over 7 years ago

TI__Guru** 116770 points

You have not indicated if this is a setup for the A15, DSP or M4 so I am going to assume it is for A15

There are multiple ways that this can be done

In the C source file:

For ARM using GCC compiler :

const int myBlock[] __attribute__((section("CUSTOM_DATA_SECTION"))) = { }

For DSP and M4 using TI Compiler

#pragma DATA_SECTION ("CUSTOM_DATA_SECTION");
const init myBlock[] = { }

In the TI RTOS configuration

Program.sectMap["CUSTOM_DATA_SECTION"] = "OCMC_RAM1";

If you want to put it at specific address you can also do:

Program.sectMap["CUSTOM_DATA_SECTION"] = new Program.SectionSpec();
Program.sectMap["CUSTOM_DATA_SECTION"].loadAddress = 0x88000000;

Check example here: e2e.ti.com/.../177186

You also have the option of adding in a linker command file to the project as long as you don`t define Memory sections which overlap with TI RTOS platform Memory map. check the map file from your RTOS project to look at what the default map looks like and then determine how your linker command needs to look like to place your custom section in it.

To disable the cache for the region, you need to configure the MMU for the region and setup MMU table to mark the region as non -cached. A good example for this is MMU setting for BoardIODelay data in the OCRAM memory which is marked non-cache normal memory. To see this configuration refer to the DeviceLoopback.cfg file in the location pdk_am57xx_1_0_xx\packages\ti\drv\mcasp\example\evmAM572x\armv7\bios

MMU setting an attributes have been described in detail in the Cortex A Programmers guide so you will not find this in the AM572x Technical reference manual.

On the last question, regarding spinlock. I checked with PCIe expert on my team on what is the recommend mechanism. It appears that typical usecase is that the PCIE Root Complex (RC) and end point (EP) generate an interrupt each other for synchronization or to indicate read/write operation is complete to the shared memory location. You may want to start by using the PCIe examples that we provide in the RTOS SDK and associated documentation available here:

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/Device_Drivers.html#pcie

Regards,

Rahul

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RTOS/AM5728: Declare Memory Block in DDR