Tool/software: Linux
On my custom board based on AM3352 - MII_1 port is connected BRCM 53101_EKMLG switch which is configured to operate in un-manged mode. Reverse MII port connected to MII_1 of AM3352
and second ethernet port MII_2 is connected to TI PHY DP83867.
At u-boot level I want either ETH_0 (from BRCM switch) or ETH_1 from TI_PHY to work.
when i do, "mii info" I can see my PHY and Switch at correct address. When I connect network cable - to Ethernet port , link and activity led is also blinking. but dhcp doesn't work. not able to acquire IP address. same for TI PHY too.
Someone can confirm my following structure are populated is ok?
Which attribute of following structuer choose which MII interface to be used by u-boot? MII_1 or MII_2 interface?
BRCM swtich support RvMII mode, so it should work in theory.
I checked my pin MUX also,
static struct module_pin_mux mii1_pin_mux[] = { /* BRCM SWITCH verified as per schematic. 11/7/18 */
{OFFSET(mii1_txclk),MODE(0) }, /* MII1_TXCLK => MII1_TCLK => PROC_FR_ES_TXC */
{OFFSET(mii1_txd0), MODE(0) }, /* MII1_TXD0 => MII1_TD0 => PROC_TO_ES_TXD0 */
{OFFSET(mii1_txd1), MODE(0) }, /* MII1_TXD1 => MII1_TD1 => PROC_TO_ES_TXD1 */
{OFFSET(mii1_txd2), MODE(0) }, /* MII1_TXD2 => MII1_TD2 => PROC_TO_ES_TXD2 */
{OFFSET(mii1_txd3), MODE(0) }, /* MII1_TXD3 => MII1_TD3 => PROC_TO_ES_TXD3 */
{OFFSET(mii1_txen), MODE(0) }, /* MII1_TXEN => MII1_TCTL => PROC_TO_ES_TXEN */
{OFFSET(mii1_rxclk), MODE(0)| RXACTIVE }, /* MII1_RXCLK => MII1_RCLK => PROC_FR_ES_RXC */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE }, /* MII1_RXD0 => MII1_RD0 => PROC_FR_ES_RXD0 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE }, /* MII1_RXD1 => MII1_RD1 => PROC_FR_ES_RXD1 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE }, /* MII1_RXD2 => MII1_RD2 => PROC_FR_ES_RXD2 */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE }, /* MII1_RXD3 => MII1_RD3 => PROC_FR_ES_RXD3 */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE }, /* MII1_RXDV => MII1_RCTL => PROC_FR_ES_RXDV */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN }, /* MDIO_CLK */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{-1},
};
//------------------------------------------------------------------------------
static struct module_pin_mux rgmii2_pin_mux[] = { /* verified as per schematic. 11/7/18 TI - GIGA PHY*/
{OFFSET(gpmc_a5), MODE(2) | PULLUDEN /*| PULLDN_EN*/ }, /* RGMII2_TD0 */
{OFFSET(gpmc_a4), MODE(2) | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_TD1 */
{OFFSET(gpmc_a3), MODE(2) | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_TD2 */
{OFFSET(gpmc_a2), MODE(2) | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_TD3 */
{OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_RD0 */
{OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_RD1 */
{OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_RD2 */
{OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_RD3 */
{OFFSET(gpmc_a6), MODE(2) | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_TCLK */
{OFFSET(gpmc_a0), MODE(2) | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_TCTL */
{OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_RCLK */
{OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLUDEN /*| PULLUP_EN*/ }, /* RGMII2_RCTL */
{-1},
};
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208, //BRCM switch. - ETH1 - MII1
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_MII,
},
{
.slave_reg_ofs = 0x308, //PROC GIGA bit PHY - ETH2 - MII2
.sliver_reg_ofs = 0xdc0,
.phy_addr = 0xC
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
.active_slave = 0,
};
