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Original question:

AM4372: power up/down sequence of VDD_CORE and VDD_MPU

AM4372: power up/down sequence

Sh.Sasaki
Guru 13625 points
Part Number: AM4372

Hi all,

I confirmed the following documents.

Discrete Power Solution for AM437x
www.tij.co.jp/.../slvuab1a.pdf

Looking at the waveform of the power down sequence of this document(P6-7),
the next sequence is executed even though the voltage has not completely fallen.

It is difficult to proceed to the next sequence after it has completely fallen to 0V during the power down sequence.

Can the device power down sequence proceed to the next sequence when the voltage drops to what voltage?

Please let me know an allowable voltage value.

Best regards,
Sasaki

  • 0
    TI__Genius 13567 points
    Hi Sasaki,
    The voltage on one supply does not need to be 0 V before the next supply can turn off. Additionally, see section 1.2 of the app note: the power-down sequence is simplified between VDDS (1.8V) and VDDSHVx (1.8V / 3.3V) supplies without any reliability concern. The important thing is to make sure PORz is asserted so the SoC is ready for the power off.

    Regards,
    Ahmad
  • 0 in reply to Ahmad_Rashed
    Guru 13625 points

    Hi Ahmad-san,

    Thank you for your support !

    Just to be sure, let me check.

    (1) Only when "Simplified Power Sequencing" is used, these(VDDS & VDDSHVx) can be simultaneously fallen without a condition. Is this correct?

    (2) If "Simplified Power Sequencing" is not used, the power down sequence is performed in reverse of the power up sequence,
         and the next falling sequence may be executed even if each voltage does not become 0V. Is this correct?

    Best regards,

    Sasaki

  • 0 in reply to Sh.Sasaki
    TI__Genius 13567 points
    1) VDDSHVx supplies at 1.8V can fall with VDDS. But VDDSHVx supplies at 3.3 must fall sooner (reverse of the power up). In any case, you wish to meet the requirement of < 2V difference between supply voltage levels mentioned in Section 5.13.1.3 Power-Down Sequencing.
    2) Yes, the requirement is VDDS voltage should not drop faster than or below the VDDSHVx voltage during the power down.

    If VDDS is supplied by an LDO and VDDSHVx is supplied by a DCDC converter, the DCDC converter voltage will decay slower than the LDO voltage and this may cause the VDDS voltage to drop faster and to drop below VDDSHVx. This is the situation you want to avoid so a discharge resistor would be needed on the DCDC converter to accelerate the ramp down.
  • 0 in reply to Ahmad_Rashed
    Guru 13625 points

    Hi Ahmad-san,

    Thank you for your support.

    I understood it.

    Best regards,

    Sasaki