Linux: RAM access between IPU1 und IPU2

Andreas Vogt57

Tool/software: Linux

Hi,

Hi,

I am using GNU Tools ARM Embedded (arm-none-eabi-gcc.exe with -march=armv7e-m) for my source code together with TI CSL drivers, I am loading the firmware via remoteproc driver in kernel.

IPU1 is located at 0x90000000 (32MB)
IPU2 is located at 0x92000000 (32MB)

I want access (read/write) from IPU1 (0x90000000) to the RAM of IPU2 (0x92000000)? Is it possible (I don't want shared RAM)? If yes, where do I need to configure it (rsc_table, dts-file, linux driver)?

Regards,

Andreas

over 6 years ago

0 Brad Griffis over 6 years ago

TI__Guru*** 125430 points

You would need to add another entry in the IPC resource table in order for the IOMMU mapping to be setup to allow access:

processors.wiki.ti.com/.../Linux_IPC_on_AM57xx

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

I tried this (with DEVMEM) but the memory content looks different (look from IPU1 at 0x92000000 != look from IPU2 at 0x92000000). Do I have to use CARVEOUT or DEVMEM in resource table for getting access to the second core RAM?

Regards
Andreas

0 Andreas Vogt57 over 6 years ago in reply to Andreas Vogt57

Intellectual 730 points

Hi,

any ideas?

Regards,
Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

CARVEOUT. Please provide some code snippets to debug. I recommend dumping the IOMMU tables like described in the wiki page.

EDIT: Actually for this particular case, a "DEVMEM" entry is more appropriate since a "carveout" actually allocates memory from CMA, but we only want that to happen once by the IPU actually using that memory. The other IPU shoud use "DEVMEM" if it wants to view that memory.

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

here how I tested it:

DTS:

   ipu1_cma_pool: ipu1_cma@90000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x0 0x90000000 0x0 0x02000000>;
                        reusable;
                        status = "okay";
                };

   ipu2_cma_pool: ipu2_cma@92000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x0 0x92000000 0x0 0x02000000>;
                        reusable;
                        status = "okay";
                };

rsc_table of IPU1 (with DEVMEM):

#define IPU_MEM_TEXT 0x00000000
#define IPU_MEM_TEXT_SIZE (SZ_1M * 1U)

#define IPU_MEM_DATA 0x90000000
#define IPU_MEM_DATA_SIZE (SZ_1M * 30U)



{
TYPE_CARVEOUT,
IPU_MEM_TEXT, 0,
IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
},

{
TYPE_CARVEOUT,
IPU_MEM_DATA, 0,
IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
},

{
TYPE_DEVMEM,
0x92000000, 0x92000000,
SZ_2M, 0, 0, "IPU_TEST_ACCESS",
},

If I use DEVMEM I can load the IPU1 firmware via remoteproc but if I look at address 0x92000000 it looks like some address table, it is not the real content of 0x92000000

If I use CARVEOUT ( I thought only a single pool can be tied to a device) I can't load IPU1 firmware via remotproc.

/ # cat /sys/kernel/debug/omap_iommu/58882000.mmu/pagetable
L:      da:     pte:
--------------------------
1: 0x00000000 0x90100002
2: 0x40300000 0x40300001
2: 0x40301000 0x40300001
2: 0x40302000 0x40300001
2: 0x40303000 0x40300001
2: 0x40304000 0x40300001
2: 0x40305000 0x40300001
2: 0x40306000 0x40300001
2: 0x40307000 0x40300001
2: 0x40308000 0x40300001
2: 0x40309000 0x40300001
2: 0x4030a000 0x40300001
2: 0x4030b000 0x40300001
2: 0x4030c000 0x40300001
2: 0x4030d000 0x40300001
2: 0x4030e000 0x40300001
2: 0x4030f000 0x40300001
2: 0x40310000 0x40310001
2: 0x40311000 0x40310001
2: 0x40312000 0x40310001
2: 0x40313000 0x40310001
2: 0x40314000 0x40310001
2: 0x40315000 0x40310001
2: 0x40316000 0x40310001
2: 0x40317000 0x40310001
2: 0x40318000 0x40310001
2: 0x40319000 0x40310001
2: 0x4031a000 0x40310001
2: 0x4031b000 0x40310001
2: 0x4031c000 0x40310001
2: 0x4031d000 0x40310001
2: 0x4031e000 0x40310001
2: 0x4031f000 0x40310001
2: 0x40320000 0x40320001
2: 0x40321000 0x40320001
2: 0x40322000 0x40320001
2: 0x40323000 0x40320001
2: 0x40324000 0x40320001
2: 0x40325000 0x40320001
2: 0x40326000 0x40320001
2: 0x40327000 0x40320001
2: 0x40328000 0x40320001
2: 0x40329000 0x40320001
2: 0x4032a000 0x40320001
2: 0x4032b000 0x40320001
2: 0x4032c000 0x40320001
2: 0x4032d000 0x40320001
2: 0x4032e000 0x40320001
2: 0x4032f000 0x40320001
2: 0x40330000 0x40330001
2: 0x40331000 0x40330001
2: 0x40332000 0x40330001
2: 0x40333000 0x40330001
2: 0x40334000 0x40330001
2: 0x40335000 0x40330001
2: 0x40336000 0x40330001
2: 0x40337000 0x40330001
2: 0x40338000 0x40330001
2: 0x40339000 0x40330001
2: 0x4033a000 0x40330001
2: 0x4033b000 0x40330001
2: 0x4033c000 0x40330001
2: 0x4033d000 0x40330001
2: 0x4033e000 0x40330001
2: 0x4033f000 0x40330001
2: 0x40340000 0x40340001
2: 0x40341000 0x40340001
2: 0x40342000 0x40340001
2: 0x40343000 0x40340001
2: 0x40344000 0x40340001
2: 0x40345000 0x40340001
2: 0x40346000 0x40340001
2: 0x40347000 0x40340001
2: 0x40348000 0x40340001
2: 0x40349000 0x40340001
2: 0x4034a000 0x40340001
2: 0x4034b000 0x40340001
2: 0x4034c000 0x40340001
2: 0x4034d000 0x40340001
2: 0x4034e000 0x40340001
2: 0x4034f000 0x40340001
2: 0x40350000 0x40350001
2: 0x40351000 0x40350001
2: 0x40352000 0x40350001
2: 0x40353000 0x40350001
2: 0x40354000 0x40350001
2: 0x40355000 0x40350001
2: 0x40356000 0x40350001
2: 0x40357000 0x40350001
2: 0x40358000 0x40350001
2: 0x40359000 0x40350001
2: 0x4035a000 0x40350001
2: 0x4035b000 0x40350001
2: 0x4035c000 0x40350001
2: 0x4035d000 0x40350001
2: 0x4035e000 0x40350001
2: 0x4035f000 0x40350001
2: 0x40360000 0x40360001
2: 0x40361000 0x40360001
2: 0x40362000 0x40360001
2: 0x40363000 0x40360001
2: 0x40364000 0x40360001
2: 0x40365000 0x40360001
2: 0x40366000 0x40360001
2: 0x40367000 0x40360001
2: 0x40368000 0x40360001
2: 0x40369000 0x40360001
2: 0x4036a000 0x40360001
2: 0x4036b000 0x40360001
2: 0x4036c000 0x40360001
2: 0x4036d000 0x40360001
2: 0x4036e000 0x40360001
2: 0x4036f000 0x40360001
2: 0x40370000 0x40370001
2: 0x40371000 0x40370001
2: 0x40372000 0x40370001
2: 0x40373000 0x40370001
2: 0x40374000 0x40370001
2: 0x40375000 0x40370001
2: 0x40376000 0x40370001
2: 0x40377000 0x40370001
2: 0x40378000 0x40370001
2: 0x40379000 0x40370001
2: 0x4037a000 0x40370001
2: 0x4037b000 0x40370001
2: 0x4037c000 0x40370001
2: 0x4037d000 0x40370001
2: 0x4037e000 0x40370001
2: 0x4037f000 0x40370001
1: 0x40400000 0x40400002
1: 0x40500000 0x40500002
1: 0x43300000 0x43300002
1: 0x43400000 0x43400002
1: 0x43500000 0x43500002
1: 0x48000000 0x48000002
1: 0x48100000 0x48100002
1: 0x48400000 0x48400002
1: 0x48500000 0x48500002
1: 0x48600000 0x48600002
1: 0x48700000 0x48700002
1: 0x48800000 0x48800002
1: 0x48900000 0x48900002
1: 0x48a00000 0x48a00002
1: 0x48b00000 0x48b00002
1: 0x48c00000 0x48c00002
1: 0x48d00000 0x48d00002
1: 0x48e00000 0x48e00002
1: 0x48f00000 0x48f00002
1: 0x4a000000 0x4a040002
1: 0x4a100000 0x4a040002
1: 0x4a200000 0x4a040002
1: 0x4a300000 0x4a040002
1: 0x4a400000 0x4a040002
1: 0x4a500000 0x4a040002
1: 0x4a600000 0x4a040002
1: 0x4a700000 0x4a040002
1: 0x4a800000 0x4a040002
1: 0x4a900000 0x4a040002
1: 0x4aa00000 0x4a040002
1: 0x4ab00000 0x4a040002
1: 0x4ac00000 0x4a040002
1: 0x4ad00000 0x4a040002
1: 0x4ae00000 0x4a040002
1: 0x4af00000 0x4a040002
1: 0x90000000 0x90200002
1: 0x90100000 0x90300002
1: 0x90200000 0x90400002
1: 0x90300000 0x90500002
1: 0x90400000 0x90600002
1: 0x90500000 0x90700002
1: 0x90600000 0x90800002
1: 0x90700000 0x90900002
1: 0x90800000 0x90a00002
1: 0x90900000 0x90b00002
1: 0x90a00000 0x90c00002
1: 0x90b00000 0x90d00002
1: 0x90c00000 0x90e00002
1: 0x90d00000 0x90f00002
1: 0x90e00000 0x91000002
1: 0x90f00000 0x91100002
1: 0x91000000 0x91200002
1: 0x91100000 0x91300002
1: 0x91200000 0x91400002
1: 0x91300000 0x91500002
1: 0x91400000 0x91600002
1: 0x91500000 0x91700002
1: 0x91600000 0x91800002
1: 0x91700000 0x91900002
1: 0x91800000 0x91a00002
1: 0x91900000 0x91b00002
1: 0x91a00000 0x91c00002
1: 0x91b00000 0x91d00002
1: 0x91c00000 0x91e00002
1: 0x91d00000 0x91f00002
1: 0x92000000 0x92000002
1: 0x92100000 0x92100002
1: 0xc0000000 0xc0000002
1: 0xc0100000 0xc0100002

Memory looks like some memory table but is is not the real content of 0x92000000:

92040000	00000000	00000200	00010002	92040200	00000000	00000200	00020002	92040400
00000000	00000200	00030002	92040600	00000000	00000200	00040002	92040800	00000000
00000200	00050002	92040A00	00000000	00000200	00060002	92040C00	00000000	00000200
00070002	92040E00	00000000	00000200	00080002	92041000	00000000	00000200	00090002
92041200	00000000	00000200	000A0002	92041400	00000000	00000200	000B0002	92041600
00000000	00000200	000C0002	92041800	00000000	00000200	000D0002	92041A00	00000000
00000200	000E0002	92041C00	00000000	00000200	000F0002	92041E00	00000000	00000200
00100002	92042000	00000000	00000200	00110002	92042200	00000000	00000200	00120002
92042400	00000000	00000200	00130002	92042600	00000000	00000200	00140002	92042800
00000000	00000200	00150002	92042A00	00000000	00000200	00160002	92042C00	00000000
00000200	00170002	92042E00	00000000	00000200	00180002	92043000	00000000	00000200
00190002	92043200	00000000	00000200	001A0002	92043400	00000000	00000200	001B0002
92043600	00000000	00000200	001C0002	92043800	00000000	00000200	001D0002	92043A00
00000000	00000200	001E0002	92043C00	00000000	00000200	001F0002	92043E00	00000000
00000200	00200002	92044000	00000000	00000200	00210002	92044200	00000000	00000200
00220002	92044400	00000000	00000200	00230002	92044600	00000000	00000200	00240002
92044800	00000000	00000200	00250002	92044A00	00000000	00000200	00260002	92044C00

If I use CARVEOUT I'm getting the following error:

[ 1167.323761] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@90000000
[ 1167.323830]  remoteproc0: 58820000.ipu is available
[ 1167.323839]  remoteproc0: Note: remoteproc is still under development and considered experimental.
[ 1167.323848]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
[ 1167.330712] cma: cma_alloc(cma c089e404, count 3, align 2)
[ 1167.330890] cma: cma_alloc(): returned ef478000
[ 1167.330941] cma: cma_alloc(cma c089e404, count 3, align 2)
[ 1167.330967] cma: cma_alloc(): returned ef478090
[ 1167.331007]  remoteproc0: powering up 58820000.ipu
[ 1167.331020]  remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 4410120
[ 1167.331140] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[ 1167.331164] cma: cma_alloc(cma c089e404, count 256, align 8)
[ 1167.331198] cma: cma_alloc(): returned ef47a400
[ 1167.331904] cma: cma_alloc(cma c089e404, count 7680, align 8)
[ 1167.332342] cma: cma_alloc(): returned ef47c800
[ 1167.352245] cma: cma_alloc(cma c089e404, count 7680, align 8)
[ 1167.352263] cma: cma_alloc(): returned   (null)
[ 1167.352276] omap-rproc 58820000.ipu: dma_alloc_coherent err: 31457280
[ 1167.352287]  remoteproc0: Failed to process resources: -12
[ 1167.353248] cma: cma_release(page ef47a400)
[ 1167.353844] cma: cma_release(page ef47c800)
[ 1167.360846]  remoteproc0: rproc_boot() failed -12
[ 1167.360864] cma: cma_release(page ef478000)
[ 1167.360883] cma: cma_release(page ef478090)
[ 1167.360914] virtio_rpmsg_bus: probe of virtio0 failed with error -12
[ 1167.360939]  remoteproc0: registered virtio0 (type 7)

Regards

Andreas

0 Andreas Vogt57 over 6 years ago in reply to Andreas Vogt57

Intellectual 730 points

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Nov 22-25 was a holiday weekend in the US. Thanks for your patience as we catch up.

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Andreas Vogt57 said:

rsc_table of IPU1 (with DEVMEM):

#define IPU_MEM_TEXT 0x00000000
#define IPU_MEM_TEXT_SIZE (SZ_1M * 1U)

#define IPU_MEM_DATA 0x90000000
#define IPU_MEM_DATA_SIZE (SZ_1M * 30U)



{
TYPE_CARVEOUT,
IPU_MEM_TEXT, 0,
IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
},

{
TYPE_CARVEOUT,
IPU_MEM_DATA, 0,
IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
},

{
TYPE_DEVMEM,
0x92000000, 0x92000000,
SZ_2M, 0, 0, "IPU_TEST_ACCESS",
},

The wiki page was primarily talking about adjusting the existing structure. Since you are adding an entry to the structure, there are a few additional pieces to it:

The second entry in the structure is equal to the number of entries in your structure. Since you're adding an entry, you need to correspondingly increment this count.
Above the resource table you'll see a bunch of structures. For example one of them is "struct fw_rsc_carveout data_cout". You will need to add a structure corresponding to your memory entry.
The fifth entry in the resource table is contains a bunch of "offsetof()" statements. You need to add one corresponding to your new structure.

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

the code above is just a snippet! I know all these configuration details and with these configurations I have the problems as described above.

I 'll send you tomorrow my complete header file for you further investigation.

But please can you answer my question in general: It is really possible to access from IPU1 (carveout) the firmware code (carveout) of IPU2?

Regards,

Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Is that also just a snippet of your pagetable output? What happened to the entries that are described in the table here:

http://processors.wiki.ti.com/index.php/Linux_IPC_on_AM57xx#Cortex_M4_IPU_Access_to_Peripherals

Keep in mind that the resource table is configuring the IOMMU. Your cfg file from the M4 is what will configure AMMU. Please share that configuration too.

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Andreas Vogt57 said:
But please can you answer my question in general: It is really possible to access from IPU1 (carveout) the firmware code (carveout) of IPU2?

Yes.

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

I will give you all files. Pagetable is not a snippet I am doing a 1 to 1 mapping (0x4a000000 <-> 0x4a000000, 0x48000000<-> 0x48000000 etc.)

Thanks for your answers the time difference is not so nice. Where are you located?

Regards
Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

I'm in the Central US time zone (UTC-6). The standard mapping for the IPU's does not perform a straight pass-through. AMMU Large Page 1 maps 0x6A00000 to 0x6A000000. Then the IOMMU is used to map from 0x6A000000 to 0x4A000000. So it is a bit surprising that your mappings do not follow this method. I was also a bit surprised to see level 2 descriptors in your table. In the past I've only seen level 1 descriptors used.

0 Brad Griffis over 6 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

Eventually we also will need to be careful about cache coherence. That will be another obstacle in terms of getting everything working perfectly.

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

enclosed the files rsc_table (with additional DEVMEM), dts file and ammu config for IPU1. For IPU2 I am using almost the same configuration but instead of address 0x90000000 I have 0x92000000.

Fullscreen ammu_init.c Download

void ammu_init(void)
{
   ammuPageConfig_t pageConfig = {0U};

   // LARGE -------------------------------------------------------
   // Mapping L4_CFG
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_LARGE;
   pageConfig.ammuPageNum     = 0U;
   pageConfig.policyRegVal    = 0x00000003; // (512MB | ENABLE)
   pageConfig.physicalAddress = 0x40000000;
   pageConfig.logicalAddress  = 0x40000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping Firmware
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_LARGE;
   pageConfig.ammuPageNum     = 1U;
   pageConfig.policyRegVal    = 0x000B0001; // (WRITE_BACK | POSTED | L1_CACHABLE | 32MB | ENABLE)
   pageConfig.physicalAddress = 0x90000000;
   pageConfig.logicalAddress  = 0x90000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping Test ADC Data
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_LARGE;
   pageConfig.ammuPageNum     = 2U;
   pageConfig.policyRegVal    = 0x00000003; // (512MB | ENABLE)
   pageConfig.physicalAddress = 0xC0000000;
   pageConfig.logicalAddress  = 0xC0000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping Firmware
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_LARGE;
   pageConfig.ammuPageNum     = 3U;
   pageConfig.policyRegVal    = 0x00000001;
   pageConfig.physicalAddress = 0x92000000;
   pageConfig.logicalAddress  = 0x92000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // MEDIUM ------------------------------------------------------
   // Mapping 1st EDMA
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_MEDIUM;
   pageConfig.ammuPageNum     = 0U;
   pageConfig.policyRegVal    = 0x00000003;
   pageConfig.physicalAddress = 0x43300000U;
   pageConfig.logicalAddress  = 0x63300000U;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping 2nd EDMA
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_MEDIUM;
   pageConfig.ammuPageNum     = 1U;
   pageConfig.policyRegVal    = 0x00000003;
   pageConfig.physicalAddress = 0x43400000U;
   pageConfig.logicalAddress  = 0x63400000U;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // SMALL --------------------------------------------------------
   // Mapping IPU_RAM: 1st 16KB
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 0U;
   pageConfig.policyRegVal    = 0x0001000B; // (L1_CACHABLE | VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55020000;
   pageConfig.logicalAddress  = 0x00000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // IPU_UNICACHE_MMU, IPU_WUGEN and IPU_MMU are placed by remoteproc at the virtual address 0x40000000
   // P.A. 0x55080000U V.A. 0x40000000U
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 1U;
   pageConfig.policyRegVal    = 0x0000000B; // (VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55080000;
   pageConfig.logicalAddress  = 0x40000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping IPU_RAM: 2nd 16KB
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 2U;
   pageConfig.policyRegVal    = 0x0001000B; // (L1_CACHABLE | VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55024000;
   pageConfig.logicalAddress  = 0x00004000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping IPU_RAM: 3nd 16KB
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 3U;
   pageConfig.policyRegVal    = 0x0001000B; // (L1_CACHABLE | VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55028000;
   pageConfig.logicalAddress  = 0x00008000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
}

Fullscreen 5280.dts.txt Download

/*
 * Copyright (C) 2018 smart microwave sensors
 * khal.culator@dothraki_school_of_mathematics.
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra76x.dtsi"
#include "dra76x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>



/ {
	model = "TI DRA762 EVM";
	compatible = "ti,dra76-evm", "ti,dra76", "ti,dra7", "sms,umrr12";

    	chosen {
                stdout-path = &uart2;
        /*        tick-timer = &timer2;*/
        };
	cpus {
		cpu@1 {
			status = "okay";
			ble-method = "spin-table";
                };

	};

   	memory {
        	device_type = "memory";
        	reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB SYSTEM RAM -> cat /proc/iomem */
    	};


	mailboxsms {
		compatible = "sms-icc-mbox";
		mboxes = <&mailbox10 &sms_mailbox>;
        	status = "okay";
	};

	/*********************************************************
         * C A R V E O U T  MEMORY CONFIGURATION                 *
	 *********************************************************/

	reserved_mem: reserved-memory {
        	#address-cells = <2>;
        	#size-cells = <2>;
        	ranges;

	        cmem_ocmc1: cmem@40300000 {
        	    compatible = "shared-dma-pool";
           	 	reg = <0x0 0x40300000 0x0 0x00080000>;
         	   	sram = <&ocmcram1>;
           	 	no-map;
            		status = "okay";
        	};

	        cmem_ocmc2: cmem@40400000 {
        	    compatible = "shared-dma-pool";
           	 	reg = <0x0 0x40400000 0x0 0x00100000>;
         	   	sram = <&ocmcram2>;
           	 	no-map;
            		status = "okay";
        	}; 

	        cmem_ocmc3: cmem@40500000 {
        	    compatible = "shared-dma-pool";
           	 	reg = <0x0 0x40500000 0x0 0x00100000>;
         	   	sram = <&ocmcram3>;
           	 	no-map;
            		status = "okay";
        	};     

                ipu1_cma_pool: ipu1_cma@90000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x0 0x90000000 0x0 0x02000000>;
                        reusable;
                        status = "okay";
                };

  		ipu2_cma_pool: ipu2_cma@92000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x0 0x92000000 0x0 0x02000000>;
                        reusable;
                        status = "okay";
                };

                dsp1_cma_pool: dsp1_cma@94000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x0 0x94000000 0x0 0x02000000>;
                        reusable;
                        status = "okay";
                };

                dsp2_cma_pool: dsp2_cma@96000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x0 0x96000000 0x0 0x02000000>;
                        reusable;
                        status = "okay";
                };

		data_pool: cmem@C0000000 {
	                compatible = "shared-dma-pool";
                        reg = <0x0 0xC0000000 0x0 0x02000000>;
           	 	no-map;
                        status = "okay";
		};
	};

   	leds {
                compatible = "gpio-leds";
		pinctrl-0 = <&pinmx_leds>;

                heartbeat {
                        label = "lin_led";
             		gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
                        default-state = "on";
                        linux,default-trigger = "heartbeat";
                };

                ipu_stat {
                        label = "ipu_led";
                        gpios = <&gpio8 8 GPIO_ACTIVE_LOW>; 
                        default-state = "off";
                };

                led1 {
                        label = "dra7:usr1";
                        gpios = <&gpio8 9 GPIO_ACTIVE_LOW>; 
                        default-state = "off";
                };

                led2 {
                        label = "dra7:usr2";
                        gpios = <&gpio8 16 GPIO_ACTIVE_LOW>; 
                        default-state = "off";
                };

                led3 {
                        label = "dra7:usr3";
                        gpios = <&gpio8 17 GPIO_ACTIVE_LOW>; 
                        default-state = "off";
                };

        };

	hw_slocks {
 		compatible = "hwspinlock-user";
        	hwlocks = 	<&hwspinlock 0>,
                  		<&hwspinlock 1>,
                  		<&hwspinlock 2>,
                  		<&hwspinlock 3>;
	};

        /* remux UART 2 and 3 */
	vsys_12v0: fixedregulator-vsys12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "vsys_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vsys_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vio_3v3: fixedregulator-vio_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vio_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	vio_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vio_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vio_3v3>;
		enable-active-high;
	};

	vio_1v8: fixedregulator-vio_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vio_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vtt_fixed: fixedregulator-vtt {
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		regulator-min-microvolt = <1350000>;
		regulator-max-microvolt = <1350000>;
		vin-supply = <&vsys_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&vio_3v3>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};
};



/* pmx steht fuer pin-multi-plex! HIER gehoeren also die Aenderungen rein... */
&dra7_pmx_core {
	pinmx_leds: pinmx_leds {
        pinctrl-single,pins = <
                        0x1fc   (PIN_OUTPUT | MUX_MODE14) /* GPIO 8_8  */
                        0x200   (PIN_OUTPUT | MUX_MODE14) /* GPIO 8_9  */
                        0x21c   (PIN_OUTPUT | MUX_MODE14) /* GPIO 8_16 */
                        0x220   (PIN_OUTPUT | MUX_MODE14) /* GPIO 8_18 */
                        0x1e0   (PIN_OUTPUT | MUX_MODE14) /* GPIO 8_1  */
                >;
	};
        pinmx_uart: pinmx_uart {
        pinctrl-single,pins = <
                        0x3f4   (PIN_INPUT_PULLUP | MUX_MODE0) /* UART2_TX */
                        0x3f0   (PIN_INPUT_PULLUP | MUX_MODE4) /* UART2_RX */

                        0x3fc   (PIN_INPUT_PULLUP | MUX_MODE14) /* UART3_TX */
                        0x3f8   (PIN_INPUT_PULLUP | MUX_MODE14) /* UART3_RX */
                >;
        };
        pinmx_can: pinmx_can {
        pinctrl-single,pins = <
                        0x3d4   (PIN_INPUT  | MUX_MODE0)
                        0x3d0   (PIN_OUTPUT | MUX_MODE0)
                >;
        };

	pinmx_i2c1: pinmx_i2c1 {
        pinctrl-single,pins = <
                        0x400   (PIN_INPUT_PULLUP | MUX_MODE0) 
                        0x404   (PIN_INPUT_PULLUP| MUX_MODE0)
                >;
        };
	pinmx_i2c3: pinmx_i2c3 {
        pinctrl-single,pins = <
                        0x2A4   (PIN_INPUT_PULLUP | MUX_MODE10)
                        0x2A8   (PIN_INPUT_PULLUP | MUX_MODE10)
                >;
        };
	pinmx_i2c4: pinmx_i2c4 {
        pinctrl-single,pins = <
                        0x2AC   (PIN_INPUT_PULLUP | MUX_MODE10)
                        0x2B0   (PIN_INPUT_PULLUP | MUX_MODE10)
                >;
        };
	pinmx_i2c5: pinmx_i2c5 {
        pinctrl-single,pins = <
                        0x2B4   (PIN_INPUT_PULLUP | MUX_MODE10)
                        0x2B8   (PIN_INPUT_PULLUP | MUX_MODE10)
                >;
        };

	cpsw_default: cpsw_default {
	pinctrl-single,pins = <
			/* Slave 2 */
			0x198 (PIN_OUTPUT | MUX_MODE3)	/* rgmii1_tclk */
			0x19c (PIN_OUTPUT | MUX_MODE3)	/* rgmii1_tctl */
			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* rgmii1_td3 */
			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* rgmii1_td2 */
			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* rgmii1_td1 */
			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* rgmii1_td0 */
			0x1b0 (PIN_INPUT  | MUX_MODE3)	/* rgmii1_rclk */
			0x1b4 (PIN_INPUT  | MUX_MODE3)	/* rgmii1_rctl */
			0x1b8 (PIN_INPUT  | MUX_MODE3)	/* rgmii1_rd3 */
			0x1bc (PIN_INPUT  | MUX_MODE3)	/* rgmii1_rd2 */
			0x1c0 (PIN_INPUT  | MUX_MODE3)	/* rgmii1_rd1 */
			0x1c4 (PIN_INPUT  | MUX_MODE3)	/* rgmii1_rd0 */
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
        pinctrl-single,pins = <
                        /* Base 0x4A003400*/
    			0x240  (PIN_INPUT_PULLUP  | MUX_MODE0)    /* mdio_data.mdio_data */
                        0x23C  (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
		>;
        };

  	i2c2_pins_i2c: pinmux_i2c2_pins_default {
                pinctrl-single,pins = <
                        0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
                        0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
                >;
        };

};

&uart1 {
	status = "okay";
};

&uart2 {
	
	pinctrl-0 = <&pinmx_uart>;
	status = "okay";
};

&uart3 {
	pinctrl-0 = <&pinmx_uart>;
	status = "okay";
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-0 = <&pinmx_i2c1>;

	/* Devices on this bus: */
	tps659038: tps659038@58 {
		/* THIS is the PMIC */
		compatible = "ti,tps659038";
		reg = <0x58>;
		ti,palmas-override-powerhold;
		ti,system-power-controller;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			regulators {
				smps123_reg: smps123 {
					/* VDD_MPU */
					regulator-name = "smps123";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE */
					regulator-name = "smps45";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_GPU - over VDD_SMPS6 */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps7_reg: smps7 {
					/* CORE_VDD */
					regulator-name = "smps7";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps8_reg: smps8 {
					/* VDD_IVAHD */
					regulator-name = "smps8";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps9_reg: smps9 {
					/* VDDS1V8 */
					regulator-name = "smps9";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo1_reg: ldo1 {
					/* LDO1_OUT --> SDIO  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo2_reg: ldo2 {
					/* VDD_RTCIO */
					/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
					regulator-name = "ldo2";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHY */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo9_reg: ldo9 {
					/* VDD_RTC */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-always-on;
					regulator-boot-on;
					regulator-allow-bypass;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				/* REGEN1 is unused */

				regen2: regen2 {
					/* Needed for PMIC internal resources */
					regulator-name = "regen2";
					regulator-boot-on;
					regulator-always-on;
				};

				/* REGEN3 is unused */

				sysen1: sysen1 {
					/* PMIC_REGEN_3V3 */
					regulator-name = "sysen1";
					regulator-boot-on;
					regulator-always-on;
				};

				sysen2: sysen2 {
					/* PMIC_REGEN_DDR */
					regulator-name = "sysen2";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
        pinctrl-0 =  <&i2c2_pins_i2c>;
	status = "okay";
	clock-frequency = <400000>;

	/* Devices on this bus: */

	i2c_rtc: rtc@32 {
		compatible = "rx8900";
		reg = <0x32>;
/*	        interrupts-extended = <&dra7_pmx_core 0x190>;  
                interrupt-names = "irq";
                wakeup-source;
*/
	};

    	eeprom: eeprom@52 {
		/* ST components: automotive EEPROM */
                compatible = "st,24c128";
                reg = <0x50>;
        };

};

&i2c3 {
	status = "okay";
	clock-frequency = <400000>;
};
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;
};
&i2c5 {
	status = "okay";
	clock-frequency = <400000>;
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&vio_3v3_sd>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is always hardwired.
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	max-frequency = <192000000>;
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&vio_1v8>;
	bus-width = <8>;
	max-frequency = <192000000>;
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr>;
	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
};

&oppdm_mpu {
};

&oppdm_dspeve {
};

&oppdm_gpu {
};

&oppdm_ivahd {
	status = "disabled";
};

&oppdm_core {
};

/* No RTC on this device */
&rtc {
	status = "disabled";
};

&mac {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_default>;
	dual_emac = <1>;
};

&cpsw_emac0 {
	status = "okay"; 
	phy_id = <&davinci_mdio>, <7>;/* PHY-ID from Micha: 0x7h */
	phy-mode = "rgmii-id";
 	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	status = "okay";
	phy_id = <&davinci_mdio>, <6>;/* PHY-ID from Micha: 0x6h */
	phy-mode = "rgmii";
 	dual_emac_res_vlan = <2>;
};

&davinci_mdio {
	status = "okay"; 
	pinctrl-names = "default";
      	pinctrl-0 = <&davinci_mdio_default>; 
};

&dcan1 {
	pinctrl-0 = <&pinmx_can>;
	status = "okay";
};


&usb2_phy1 {
	phy-supply = <&ldo3_reg>;
	status = "disabled";
};

&usb2_phy2 {
	phy-supply = <&ldo3_reg>;
	status = "disabled";
};
&dss {
	status = "disabled";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		status = "disabled";

		port@lcd3 {
			reg = <2>;

			dpi_out3: endpoint {
				data-lines = <24>;
			};
		};
	};
};

&hdmi {
	status = "disabled";
};

&qspi {
	spi-max-frequency = <96000000>;
	status = "disabled";
	m25p80@0 {
		spi-max-frequency = <96000000>;
	};
};

&pcie2_phy {
	status = "disabled";
};

&pcie1_rc {
	num-lanes = <2>;
	phys = <&pcie1_phy>, <&pcie2_phy>;
	phy-names = "pcie-phy0", "pcie-phy1";
	status = "disabled";
};

/* Activate SUB-Cores: */
&mmu0_dsp1 {
        status = "okay";
};

&mmu1_dsp1 {
        status = "okay";
};

&mmu0_dsp2 {
        status = "okay";
};

&mmu1_dsp2 {
        status = "okay";
};

&mmu_ipu1 {
        status = "okay";
};

&mmu_ipu2 {
        status = "okay";
};

&ipu2 {
        mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
};

&ipu1 {
 	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
};

&dsp2 {
	status = "okay";
	memory-region = <&dsp2_cma_pool>;
};

&mailbox3 {
        status = "okay";
        mbox_pru1_0: mbox_pru1_0 {
        status = "okay";
        };
        mbox_pru1_1: mbox_pru1_1 {
        status = "okay";
        };
};

&mailbox4 {
        status = "okay";
        mbox_pru2_0: mbox_pru2_0 {
        status = "okay";
        };
        mbox_pru2_1: mbox_pru2_1 {
        status = "okay";
       	};
};

&mailbox5 {
        status = "okay";
        mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
                status = "okay";
        };
        mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
                status = "okay";
        };
};

&mailbox6 {
        status = "okay";
        mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
                status = "okay";
        };
        mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
                status = "okay";
        };
};

&mailbox10 {
        status = "okay";
        sms_mailbox:sms_mailbox {
        ti,mbox-tx = <0 0 0>;       /* M10 Q1: RX beim M4 */
        ti,mbox-rx = <1 0 0>;       /* M10 Q0: TX beim M4 */
        status = "okay";
    };
};
&timer2 {
        status = "disabled";
};
&timer3 {
        status = "okay";
};

/* Linux uses first 32 channels, BIOS uses last 32 */
&edma {

	ti,edma-reserved-slot-ranges = <35 10>;
        dma-requests = <32>;
        ti,edma-reserved-slot-ranges = <35 10>;
};

rsc_table_ipu1.h

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

I wanted to send you this info sooner, but I had to debug an issue related to it first. There's a feature I added to the omapconf utility last year that parses all the IPU AMMU entries. I was having trouble getting it to work with the SDK, and I finally realized that the SDK is building an older version of the utility. So I have now rebuilt omapconf with the latest sources. I have a binary that I am sharing on Box here:

https://txn.box.com/s/udj9vmtjf7tbb8up8o5c2roh89raop12

Unfortunately for others that might stumble across this post, that link expires on Dec 4th. I've also sent a patch to our SDK team such that our Yocto build will pick up this latest version, so hopefully that will be integrated shortly and this omapconf will be automatically included in future SDK's.

So in any case, if you can download that omapconf build and replace the omapconf in your file system, you can run a command like this:

root@am57xx-evm:/mnt/scratch# omapconf show ammu > ammu-decode.txt

Please attach the corresponding ammu-decode.txt file. This will give us a clear view of what's happening since it will be reflecting the actual hardware and not just my interpretation of your code. (Though the ammu code looks very clean from looking at your C code.) On first glance it looks like you have appropriate mappings in place, though I would like to review the decoded output.

I'm about to look at your rsc_table_ipu1.h now...

0 Brad Griffis over 6 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

Your resource table has been derived from the wrong file. It should be derived from rsc_table_vayu_ipu.h, but yours appears to have come from rsc_table_omap5_ipu.h.

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

thanks I will give you the output of the ammu later.

Please can you give me some more details why do you think that the file was derived from the wrong rsc_table?
I can not see many differences between the files!

Andreas

0 Andreas Vogt57 over 6 years ago in reply to Andreas Vogt57

Intellectual 730 points

Hi,

ammu-decode_norm.txt: is without extra devmem/ammu entry for accessing IPU2 from IPU1

ammu-decode_devm.txt: is with extra devmem/ammu entry for acccessing IPU2 frrom IPU1:

additional I get some error:

/ # omapconf show ammu > ammu-decode_devm.txt
Error: I2C Read failed
Error: I2C Read failed
Error: I2C Read failed
release_details_get(): could not open /etc/issue.net file?!

and it seems that some entries are double in the txt-file.

Fullscreen ammu-decode_norm.txt Download

OMAPCONF (rev v1.73-19-gbe8626b built Tue Nov 27 22:27:21 UTC 2018)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA76X ES1.0 GP Device (STANDARD performance (1.8GHz))
  UNKNOWN POWER IC

SW Build Details:
  Build:
    Version: UNKNOWN
  Kernel:
    Version: 4.4.84-SMS_MONOLYTHIC-svn53
    Author: tdax@avo-VirtualBox
    Toolchain: gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1)
    Type: #44 SMP PREEMPT
    Date: Fri Nov 23 08:28:15 CET 2018

**************************************************
******   Decoding AMMU Mappings for IPU1    ******
**************************************************

*** Decoding Large Page 0  ***
CACHE_MMU_LARGE_ADDR_0 = 0x40000000
CACHE_MMU_LARGE_XLTE_0 = 0x40000000
CACHE_MMU_LARGE_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x40000000 - 0x5FFFFFFF
Physical address = 0x40000000 - 0x5FFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 1  ***
CACHE_MMU_LARGE_ADDR_1 = 0x90000000
CACHE_MMU_LARGE_XLTE_1 = 0x90000000
CACHE_MMU_LARGE_POLICY_1 = 0x000B0001

PAGE ENABLED
Logical Address  = 0x90000000 - 0x91FFFFFF
Physical address = 0x90000000 - 0x91FFFFFF
Policy
 * L1 write policy is writeback
 * L1 allocate policy: no writes allocated
 * L1 writes posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Large Page 2  ***
CACHE_MMU_LARGE_ADDR_2 = 0xC0000000
CACHE_MMU_LARGE_XLTE_2 = 0xC0000000
CACHE_MMU_LARGE_POLICY_2 = 0x00000003

PAGE ENABLED
Logical Address  = 0xC0000000 - 0xDFFFFFFF
Physical address = 0xC0000000 - 0xDFFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 3  ***
CACHE_MMU_LARGE_ADDR_3 = 0x00000000
CACHE_MMU_LARGE_XLTE_3 = 0x00000000
CACHE_MMU_LARGE_POLICY_3 = 0x00000000

PAGE NOT ENABLED

*** Decoding Medium Page 0  ***
CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000
CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000
CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63300000 - 0x6333FFFF
Physical address = 0x43300000 - 0x4333FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Medium Page 1  ***
CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000
CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000
CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63400000 - 0x6343FFFF
Physical address = 0x43400000 - 0x4343FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Small Page 0  ***
CACHE_MMU_SMALL_ADDR_0 = 0x00000000
CACHE_MMU_SMALL_XLTE_0 = 0x55020000
CACHE_MMU_SMALL_POLICY_0 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00000000 - 0x00003FFF
Physical address = 0x55020000 - 0x55023FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 1  ***
CACHE_MMU_SMALL_ADDR_1 = 0x40000000
CACHE_MMU_SMALL_XLTE_1 = 0x55080000
CACHE_MMU_SMALL_POLICY_1 = 0x0000000B

PAGE ENABLED
Logical Address  = 0x40000000 - 0x40003FFF
Physical address = 0x55080000 - 0x55083FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 2  ***
CACHE_MMU_SMALL_ADDR_2 = 0x00004000
CACHE_MMU_SMALL_XLTE_2 = 0x55024000
CACHE_MMU_SMALL_POLICY_2 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00004000 - 0x00007FFF
Physical address = 0x55024000 - 0x55027FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 3  ***
CACHE_MMU_SMALL_ADDR_3 = 0x00008000
CACHE_MMU_SMALL_XLTE_3 = 0x55028000
CACHE_MMU_SMALL_POLICY_3 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00008000 - 0x0000BFFF
Physical address = 0x55028000 - 0x5502BFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 4  ***
CACHE_MMU_SMALL_ADDR_4 = 0x00000000
CACHE_MMU_SMALL_XLTE_4 = 0x00000000
CACHE_MMU_SMALL_POLICY_4 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 5  ***
CACHE_MMU_SMALL_ADDR_5 = 0x00000000
CACHE_MMU_SMALL_XLTE_5 = 0x00000000
CACHE_MMU_SMALL_POLICY_5 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 6  ***
CACHE_MMU_SMALL_ADDR_6 = 0x00000000
CACHE_MMU_SMALL_XLTE_6 = 0x00000000
CACHE_MMU_SMALL_POLICY_6 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 7  ***
CACHE_MMU_SMALL_ADDR_7 = 0x00000000
CACHE_MMU_SMALL_XLTE_7 = 0x00000000
CACHE_MMU_SMALL_POLICY_7 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 8  ***
CACHE_MMU_SMALL_ADDR_8 = 0x00000000
CACHE_MMU_SMALL_XLTE_8 = 0x00000000
CACHE_MMU_SMALL_POLICY_8 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 9  ***
CACHE_MMU_SMALL_ADDR_9 = 0x00000000
CACHE_MMU_SMALL_XLTE_9 = 0x00000000
CACHE_MMU_SMALL_POLICY_9 = 0x00000000

PAGE NOT ENABLED

**************************************************
******   Decoding AMMU Mappings for IPU2    ******
**************************************************

*** Decoding Large Page 0  ***
CACHE_MMU_LARGE_ADDR_0 = 0x40000000
CACHE_MMU_LARGE_XLTE_0 = 0x40000000
CACHE_MMU_LARGE_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x40000000 - 0x5FFFFFFF
Physical address = 0x40000000 - 0x5FFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 1  ***
CACHE_MMU_LARGE_ADDR_1 = 0x92000000
CACHE_MMU_LARGE_XLTE_1 = 0x92000000
CACHE_MMU_LARGE_POLICY_1 = 0x000B0001

PAGE ENABLED
Logical Address  = 0x92000000 - 0x93FFFFFF
Physical address = 0x92000000 - 0x93FFFFFF
Policy
 * L1 write policy is writeback
 * L1 allocate policy: no writes allocated
 * L1 writes posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Large Page 2  ***
CACHE_MMU_LARGE_ADDR_2 = 0xC0000000
CACHE_MMU_LARGE_XLTE_2 = 0xC0000000
CACHE_MMU_LARGE_POLICY_2 = 0x00000003

PAGE ENABLED
Logical Address  = 0xC0000000 - 0xDFFFFFFF
Physical address = 0xC0000000 - 0xDFFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 3  ***
CACHE_MMU_LARGE_ADDR_3 = 0x00000000
CACHE_MMU_LARGE_XLTE_3 = 0x00000000
CACHE_MMU_LARGE_POLICY_3 = 0x00000000

PAGE NOT ENABLED

*** Decoding Medium Page 0  ***
CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000
CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000
CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63300000 - 0x6333FFFF
Physical address = 0x43300000 - 0x4333FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Medium Page 1  ***
CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000
CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000
CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63400000 - 0x6343FFFF
Physical address = 0x43400000 - 0x4343FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Small Page 0  ***
CACHE_MMU_SMALL_ADDR_0 = 0x00000000
CACHE_MMU_SMALL_XLTE_0 = 0x55020000
CACHE_MMU_SMALL_POLICY_0 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00000000 - 0x00003FFF
Physical address = 0x55020000 - 0x55023FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 1  ***
CACHE_MMU_SMALL_ADDR_1 = 0x40000000
CACHE_MMU_SMALL_XLTE_1 = 0x55080000
CACHE_MMU_SMALL_POLICY_1 = 0x0000000B

PAGE ENABLED
Logical Address  = 0x40000000 - 0x40003FFF
Physical address = 0x55080000 - 0x55083FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 2  ***
CACHE_MMU_SMALL_ADDR_2 = 0x00004000
CACHE_MMU_SMALL_XLTE_2 = 0x55024000
CACHE_MMU_SMALL_POLICY_2 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00004000 - 0x00007FFF
Physical address = 0x55024000 - 0x55027FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 3  ***
CACHE_MMU_SMALL_ADDR_3 = 0x00008000
CACHE_MMU_SMALL_XLTE_3 = 0x55028000
CACHE_MMU_SMALL_POLICY_3 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00008000 - 0x0000BFFF
Physical address = 0x55028000 - 0x5502BFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 4  ***
CACHE_MMU_SMALL_ADDR_4 = 0x00000000
CACHE_MMU_SMALL_XLTE_4 = 0x00000000
CACHE_MMU_SMALL_POLICY_4 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 5  ***
CACHE_MMU_SMALL_ADDR_5 = 0x00000000
CACHE_MMU_SMALL_XLTE_5 = 0x00000000
CACHE_MMU_SMALL_POLICY_5 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 6  ***
CACHE_MMU_SMALL_ADDR_6 = 0x00000000
CACHE_MMU_SMALL_XLTE_6 = 0x00000000
CACHE_MMU_SMALL_POLICY_6 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 7  ***
CACHE_MMU_SMALL_ADDR_7 = 0x00000000
CACHE_MMU_SMALL_XLTE_7 = 0x00000000
CACHE_MMU_SMALL_POLICY_7 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 8  ***
CACHE_MMU_SMALL_ADDR_8 = 0x00000000
CACHE_MMU_SMALL_XLTE_8 = 0x00000000
CACHE_MMU_SMALL_POLICY_8 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 9  ***
CACHE_MMU_SMALL_ADDR_9 = 0x00000000
CACHE_MMU_SMALL_XLTE_9 = 0x00000000
CACHE_MMU_SMALL_POLICY_9 = 0x00000000

PAGE NOT ENABLED

*** Decoding Large Page 0  ***
CACHE_MMU_LARGE_ADDR_0 = 0x40000000
CACHE_MMU_LARGE_XLTE_0 = 0x40000000
CACHE_MMU_LARGE_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x40000000 - 0x5FFFFFFF
Physical address = 0x40000000 - 0x5FFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 1  ***
CACHE_MMU_LARGE_ADDR_1 = 0x90000000
CACHE_MMU_LARGE_XLTE_1 = 0x90000000
CACHE_MMU_LARGE_POLICY_1 = 0x000B0001

PAGE ENABLED
Logical Address  = 0x90000000 - 0x91FFFFFF
Physical address = 0x90000000 - 0x91FFFFFF
Policy
 * L1 write policy is writeback
 * L1 allocate policy: no writes allocated
 * L1 writes posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Large Page 2  ***
CACHE_MMU_LARGE_ADDR_2 = 0xC0000000
CACHE_MMU_LARGE_XLTE_2 = 0xC0000000
CACHE_MMU_LARGE_POLICY_2 = 0x00000003

PAGE ENABLED
Logical Address  = 0xC0000000 - 0xDFFFFFFF
Physical address = 0xC0000000 - 0xDFFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 3  ***
CACHE_MMU_LARGE_ADDR_3 = 0x00000000
CACHE_MMU_LARGE_XLTE_3 = 0x00000000
CACHE_MMU_LARGE_POLICY_3 = 0x00000000

PAGE NOT ENABLED

*** Decoding Medium Page 0  ***
CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000
CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000
CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63300000 - 0x6333FFFF
Physical address = 0x43300000 - 0x4333FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Medium Page 1  ***
CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000
CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000
CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63400000 - 0x6343FFFF
Physical address = 0x43400000 - 0x4343FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Small Page 0  ***
CACHE_MMU_SMALL_ADDR_0 = 0x00000000
CACHE_MMU_SMALL_XLTE_0 = 0x55020000
CACHE_MMU_SMALL_POLICY_0 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00000000 - 0x00003FFF
Physical address = 0x55020000 - 0x55023FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 1  ***
CACHE_MMU_SMALL_ADDR_1 = 0x40000000
CACHE_MMU_SMALL_XLTE_1 = 0x55080000
CACHE_MMU_SMALL_POLICY_1 = 0x0000000B

PAGE ENABLED
Logical Address  = 0x40000000 - 0x40003FFF
Physical address = 0x55080000 - 0x55083FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 2  ***
CACHE_MMU_SMALL_ADDR_2 = 0x00004000
CACHE_MMU_SMALL_XLTE_2 = 0x55024000
CACHE_MMU_SMALL_POLICY_2 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00004000 - 0x00007FFF
Physical address = 0x55024000 - 0x55027FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 3  ***
CACHE_MMU_SMALL_ADDR_3 = 0x00008000
CACHE_MMU_SMALL_XLTE_3 = 0x55028000
CACHE_MMU_SMALL_POLICY_3 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00008000 - 0x0000BFFF
Physical address = 0x55028000 - 0x5502BFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 4  ***
CACHE_MMU_SMALL_ADDR_4 = 0x00000000
CACHE_MMU_SMALL_XLTE_4 = 0x00000000
CACHE_MMU_SMALL_POLICY_4 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 5  ***
CACHE_MMU_SMALL_ADDR_5 = 0x00000000
CACHE_MMU_SMALL_XLTE_5 = 0x00000000
CACHE_MMU_SMALL_POLICY_5 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 6  ***
CACHE_MMU_SMALL_ADDR_6 = 0x00000000
CACHE_MMU_SMALL_XLTE_6 = 0x00000000
CACHE_MMU_SMALL_POLICY_6 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 7  ***
CACHE_MMU_SMALL_ADDR_7 = 0x00000000
CACHE_MMU_SMALL_XLTE_7 = 0x00000000
CACHE_MMU_SMALL_POLICY_7 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 8  ***
CACHE_MMU_SMALL_ADDR_8 = 0x00000000
CACHE_MMU_SMALL_XLTE_8 = 0x00000000
CACHE_MMU_SMALL_POLICY_8 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 9  ***
CACHE_MMU_SMALL_ADDR_9 = 0x00000000
CACHE_MMU_SMALL_XLTE_9 = 0x00000000
CACHE_MMU_SMALL_POLICY_9 = 0x00000000

PAGE NOT ENABLED

Fullscreen ammu-decode_devm.txt Download

OMAPCONF (rev v1.73-19-gbe8626b built Tue Nov 27 22:27:21 UTC 2018)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA76X ES1.0 GP Device (STANDARD performance (1.8GHz))
  UNKNOWN POWER IC

SW Build Details:
  Build:
    Version: UNKNOWN
  Kernel:
    Version: 4.4.84-SMS_MONOLYTHIC-svn53
    Author: tdax@avo-VirtualBox
    Toolchain: gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1)
    Type: #44 SMP PREEMPT
    Date: Fri Nov 23 08:28:15 CET 2018

**************************************************
******   Decoding AMMU Mappings for IPU1    ******
**************************************************

*** Decoding Large Page 0  ***
CACHE_MMU_LARGE_ADDR_0 = 0x40000000
CACHE_MMU_LARGE_XLTE_0 = 0x40000000
CACHE_MMU_LARGE_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x40000000 - 0x5FFFFFFF
Physical address = 0x40000000 - 0x5FFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 1  ***
CACHE_MMU_LARGE_ADDR_1 = 0x90000000
CACHE_MMU_LARGE_XLTE_1 = 0x90000000
CACHE_MMU_LARGE_POLICY_1 = 0x000B0001

PAGE ENABLED
Logical Address  = 0x90000000 - 0x91FFFFFF
Physical address = 0x90000000 - 0x91FFFFFF
Policy
 * L1 write policy is writeback
 * L1 allocate policy: no writes allocated
 * L1 writes posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Large Page 2  ***
CACHE_MMU_LARGE_ADDR_2 = 0xC0000000
CACHE_MMU_LARGE_XLTE_2 = 0xC0000000
CACHE_MMU_LARGE_POLICY_2 = 0x00000003

PAGE ENABLED
Logical Address  = 0xC0000000 - 0xDFFFFFFF
Physical address = 0xC0000000 - 0xDFFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 3  ***
CACHE_MMU_LARGE_ADDR_3 = 0x92000000
CACHE_MMU_LARGE_XLTE_3 = 0x92000000
CACHE_MMU_LARGE_POLICY_3 = 0x00000001

PAGE ENABLED
Logical Address  = 0x92000000 - 0x93FFFFFF
Physical address = 0x92000000 - 0x93FFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Medium Page 0  ***
CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000
CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000
CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63300000 - 0x6333FFFF
Physical address = 0x43300000 - 0x4333FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Medium Page 1  ***
CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000
CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000
CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63400000 - 0x6343FFFF
Physical address = 0x43400000 - 0x4343FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Small Page 0  ***
CACHE_MMU_SMALL_ADDR_0 = 0x00000000
CACHE_MMU_SMALL_XLTE_0 = 0x55020000
CACHE_MMU_SMALL_POLICY_0 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00000000 - 0x00003FFF
Physical address = 0x55020000 - 0x55023FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 1  ***
CACHE_MMU_SMALL_ADDR_1 = 0x40000000
CACHE_MMU_SMALL_XLTE_1 = 0x55080000
CACHE_MMU_SMALL_POLICY_1 = 0x0000000B

PAGE ENABLED
Logical Address  = 0x40000000 - 0x40003FFF
Physical address = 0x55080000 - 0x55083FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 2  ***
CACHE_MMU_SMALL_ADDR_2 = 0x00004000
CACHE_MMU_SMALL_XLTE_2 = 0x55024000
CACHE_MMU_SMALL_POLICY_2 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00004000 - 0x00007FFF
Physical address = 0x55024000 - 0x55027FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 3  ***
CACHE_MMU_SMALL_ADDR_3 = 0x00008000
CACHE_MMU_SMALL_XLTE_3 = 0x55028000
CACHE_MMU_SMALL_POLICY_3 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00008000 - 0x0000BFFF
Physical address = 0x55028000 - 0x5502BFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 4  ***
CACHE_MMU_SMALL_ADDR_4 = 0x00000000
CACHE_MMU_SMALL_XLTE_4 = 0x00000000
CACHE_MMU_SMALL_POLICY_4 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 5  ***
CACHE_MMU_SMALL_ADDR_5 = 0x00000000
CACHE_MMU_SMALL_XLTE_5 = 0x00000000
CACHE_MMU_SMALL_POLICY_5 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 6  ***
CACHE_MMU_SMALL_ADDR_6 = 0x00000000
CACHE_MMU_SMALL_XLTE_6 = 0x00000000
CACHE_MMU_SMALL_POLICY_6 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 7  ***
CACHE_MMU_SMALL_ADDR_7 = 0x00000000
CACHE_MMU_SMALL_XLTE_7 = 0x00000000
CACHE_MMU_SMALL_POLICY_7 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 8  ***
CACHE_MMU_SMALL_ADDR_8 = 0x00000000
CACHE_MMU_SMALL_XLTE_8 = 0x00000000
CACHE_MMU_SMALL_POLICY_8 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 9  ***
CACHE_MMU_SMALL_ADDR_9 = 0x00000000
CACHE_MMU_SMALL_XLTE_9 = 0x00000000
CACHE_MMU_SMALL_POLICY_9 = 0x00000000

PAGE NOT ENABLED

**************************************************
******   Decoding AMMU Mappings for IPU2    ******
**************************************************

*** Decoding Large Page 0  ***
CACHE_MMU_LARGE_ADDR_0 = 0x40000000
CACHE_MMU_LARGE_XLTE_0 = 0x40000000
CACHE_MMU_LARGE_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x40000000 - 0x5FFFFFFF
Physical address = 0x40000000 - 0x5FFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 1  ***
CACHE_MMU_LARGE_ADDR_1 = 0x92000000
CACHE_MMU_LARGE_XLTE_1 = 0x92000000
CACHE_MMU_LARGE_POLICY_1 = 0x000B0001

PAGE ENABLED
Logical Address  = 0x92000000 - 0x93FFFFFF
Physical address = 0x92000000 - 0x93FFFFFF
Policy
 * L1 write policy is writeback
 * L1 allocate policy: no writes allocated
 * L1 writes posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Large Page 2  ***
CACHE_MMU_LARGE_ADDR_2 = 0xC0000000
CACHE_MMU_LARGE_XLTE_2 = 0xC0000000
CACHE_MMU_LARGE_POLICY_2 = 0x00000003

PAGE ENABLED
Logical Address  = 0xC0000000 - 0xDFFFFFFF
Physical address = 0xC0000000 - 0xDFFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 3  ***
CACHE_MMU_LARGE_ADDR_3 = 0x00000000
CACHE_MMU_LARGE_XLTE_3 = 0x00000000
CACHE_MMU_LARGE_POLICY_3 = 0x00000000

PAGE NOT ENABLED

*** Decoding Medium Page 0  ***
CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000
CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000
CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63300000 - 0x6333FFFF
Physical address = 0x43300000 - 0x4333FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Medium Page 1  ***
CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000
CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000
CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63400000 - 0x6343FFFF
Physical address = 0x43400000 - 0x4343FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Small Page 0  ***
CACHE_MMU_SMALL_ADDR_0 = 0x00000000
CACHE_MMU_SMALL_XLTE_0 = 0x55020000
CACHE_MMU_SMALL_POLICY_0 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00000000 - 0x00003FFF
Physical address = 0x55020000 - 0x55023FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 1  ***
CACHE_MMU_SMALL_ADDR_1 = 0x40000000
CACHE_MMU_SMALL_XLTE_1 = 0x55080000
CACHE_MMU_SMALL_POLICY_1 = 0x0000000B

PAGE ENABLED
Logical Address  = 0x40000000 - 0x40003FFF
Physical address = 0x55080000 - 0x55083FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 2  ***
CACHE_MMU_SMALL_ADDR_2 = 0x00004000
CACHE_MMU_SMALL_XLTE_2 = 0x55024000
CACHE_MMU_SMALL_POLICY_2 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00004000 - 0x00007FFF
Physical address = 0x55024000 - 0x55027FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 3  ***
CACHE_MMU_SMALL_ADDR_3 = 0x00008000
CACHE_MMU_SMALL_XLTE_3 = 0x55028000
CACHE_MMU_SMALL_POLICY_3 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00008000 - 0x0000BFFF
Physical address = 0x55028000 - 0x5502BFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 4  ***
CACHE_MMU_SMALL_ADDR_4 = 0x00000000
CACHE_MMU_SMALL_XLTE_4 = 0x00000000
CACHE_MMU_SMALL_POLICY_4 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 5  ***
CACHE_MMU_SMALL_ADDR_5 = 0x00000000
CACHE_MMU_SMALL_XLTE_5 = 0x00000000
CACHE_MMU_SMALL_POLICY_5 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 6  ***
CACHE_MMU_SMALL_ADDR_6 = 0x00000000
CACHE_MMU_SMALL_XLTE_6 = 0x00000000
CACHE_MMU_SMALL_POLICY_6 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 7  ***
CACHE_MMU_SMALL_ADDR_7 = 0x00000000
CACHE_MMU_SMALL_XLTE_7 = 0x00000000
CACHE_MMU_SMALL_POLICY_7 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 8  ***
CACHE_MMU_SMALL_ADDR_8 = 0x00000000
CACHE_MMU_SMALL_XLTE_8 = 0x00000000
CACHE_MMU_SMALL_POLICY_8 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 9  ***
CACHE_MMU_SMALL_ADDR_9 = 0x00000000
CACHE_MMU_SMALL_XLTE_9 = 0x00000000
CACHE_MMU_SMALL_POLICY_9 = 0x00000000

PAGE NOT ENABLED

*** Decoding Large Page 0  ***
CACHE_MMU_LARGE_ADDR_0 = 0x40000000
CACHE_MMU_LARGE_XLTE_0 = 0x40000000
CACHE_MMU_LARGE_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x40000000 - 0x5FFFFFFF
Physical address = 0x40000000 - 0x5FFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 1  ***
CACHE_MMU_LARGE_ADDR_1 = 0x90000000
CACHE_MMU_LARGE_XLTE_1 = 0x90000000
CACHE_MMU_LARGE_POLICY_1 = 0x000B0001

PAGE ENABLED
Logical Address  = 0x90000000 - 0x91FFFFFF
Physical address = 0x90000000 - 0x91FFFFFF
Policy
 * L1 write policy is writeback
 * L1 allocate policy: no writes allocated
 * L1 writes posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Large Page 2  ***
CACHE_MMU_LARGE_ADDR_2 = 0xC0000000
CACHE_MMU_LARGE_XLTE_2 = 0xC0000000
CACHE_MMU_LARGE_POLICY_2 = 0x00000003

PAGE ENABLED
Logical Address  = 0xC0000000 - 0xDFFFFFFF
Physical address = 0xC0000000 - 0xDFFFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 512 MB page

*** Decoding Large Page 3  ***
CACHE_MMU_LARGE_ADDR_3 = 0x92000000
CACHE_MMU_LARGE_XLTE_3 = 0x92000000
CACHE_MMU_LARGE_POLICY_3 = 0x00000001

PAGE ENABLED
Logical Address  = 0x92000000 - 0x93FFFFFF
Physical address = 0x92000000 - 0x93FFFFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 32 MB page

*** Decoding Medium Page 0  ***
CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000
CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000
CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63300000 - 0x6333FFFF
Physical address = 0x43300000 - 0x4333FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Medium Page 1  ***
CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000
CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000
CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003

PAGE ENABLED
Logical Address  = 0x63400000 - 0x6343FFFF
Physical address = 0x43400000 - 0x4343FFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Do not follow volatile qualifier
 * 256 KB page

*** Decoding Small Page 0  ***
CACHE_MMU_SMALL_ADDR_0 = 0x00000000
CACHE_MMU_SMALL_XLTE_0 = 0x55020000
CACHE_MMU_SMALL_POLICY_0 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00000000 - 0x00003FFF
Physical address = 0x55020000 - 0x55023FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 1  ***
CACHE_MMU_SMALL_ADDR_1 = 0x40000000
CACHE_MMU_SMALL_XLTE_1 = 0x55080000
CACHE_MMU_SMALL_POLICY_1 = 0x0000000B

PAGE ENABLED
Logical Address  = 0x40000000 - 0x40003FFF
Physical address = 0x55080000 - 0x55083FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 noncacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 2  ***
CACHE_MMU_SMALL_ADDR_2 = 0x00004000
CACHE_MMU_SMALL_XLTE_2 = 0x55024000
CACHE_MMU_SMALL_POLICY_2 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00004000 - 0x00007FFF
Physical address = 0x55024000 - 0x55027FFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 3  ***
CACHE_MMU_SMALL_ADDR_3 = 0x00008000
CACHE_MMU_SMALL_XLTE_3 = 0x55028000
CACHE_MMU_SMALL_POLICY_3 = 0x0001000B

PAGE ENABLED
Logical Address  = 0x00008000 - 0x0000BFFF
Physical address = 0x55028000 - 0x5502BFFF
Policy
 * L1 write policy is writethrough
 * L1 allocate policy: no writes allocated
 * L1 writes non-posted
 * L1 cacheable
 * Do not send cache exclusion sideband
 * Preload disabled
 * Read/Write
 * Read/Write/Execute
 * Follow volatile qualifier
 * 16 KB page

*** Decoding Small Page 4  ***
CACHE_MMU_SMALL_ADDR_4 = 0x00000000
CACHE_MMU_SMALL_XLTE_4 = 0x00000000
CACHE_MMU_SMALL_POLICY_4 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 5  ***
CACHE_MMU_SMALL_ADDR_5 = 0x00000000
CACHE_MMU_SMALL_XLTE_5 = 0x00000000
CACHE_MMU_SMALL_POLICY_5 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 6  ***
CACHE_MMU_SMALL_ADDR_6 = 0x00000000
CACHE_MMU_SMALL_XLTE_6 = 0x00000000
CACHE_MMU_SMALL_POLICY_6 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 7  ***
CACHE_MMU_SMALL_ADDR_7 = 0x00000000
CACHE_MMU_SMALL_XLTE_7 = 0x00000000
CACHE_MMU_SMALL_POLICY_7 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 8  ***
CACHE_MMU_SMALL_ADDR_8 = 0x00000000
CACHE_MMU_SMALL_XLTE_8 = 0x00000000
CACHE_MMU_SMALL_POLICY_8 = 0x00000000

PAGE NOT ENABLED

*** Decoding Small Page 9  ***
CACHE_MMU_SMALL_ADDR_9 = 0x00000000
CACHE_MMU_SMALL_XLTE_9 = 0x00000000
CACHE_MMU_SMALL_POLICY_9 = 0x00000000

PAGE NOT ENABLED

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

This comment is in your code:

custom_rsc_table_omap5_ipu.h

Plus the copyright in the header says 2013 and the number of entries in the table is 13. Maybe you mistakenly attached the wrong file to e2e?

I’ll be able to review the AMMU a bit later.

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

no I attached the correct file to e2e. But I think, that comments and copyright header doesn't have much influence on the running system, right? :)
If you make a diff between my rsc_table and vayu's rsc_table there isn't much fundamental difference except that I am using different subcore addresses and less entries (13) cause I don't need them (keep it simple keep it small).

Regards,
Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Andreas,

Given all the places that things can go wrong, the recommended procedure is to start with a known good piece of software and make incremental changes. So in my opinion, starting from the proper resource table (vayu) is quite critical. In order for me to fully review the files you've provided, I would need to do a 3-way diff using the original omap5 file to see what changes you've made there, as well as the vayu file to see what we might be missing from there. It is far more complex than simply providing a delta of what you changed in the vayu file.

For now, I think our best bet is to leverage the omapconf ammu decoding plus the Linux IOMMU page table dump in order to see if things are configured properly. I'm going to have a look at your AMMU decoding and provide some further inputs.

Brad

0 Brad Griffis over 6 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

One other important question... Is your code functioning currrently on both IPU's? We should have that fully operational before we attempt to make further changes. I have been assuming you had that working, but I'd like to verify.

I see an issue in your AMMU mappings. You've configured Large Page 1 as follows:

IPU1: Unity mapping of 0x90000000 - 0x91FFFFFF
IPU2: Unity mapping of 0x92000000 - 0x93FFFFFF

This mapping allows IPU1 to see its own carveout and it allows IPU2 to see its own carveout. That's good (necessary!). However, I don't see any mappings related to the other IPU cores. Specifically, you would need to add the following mappings:

IPU1: Unity mapping of 0x92000000 - 0x93FFFFFF
IPU2: Unity mapping of 0x90000000 - 0x91FFFFFF

I'm separately looking at some of the IOMMU mappings. Though in general I like to start at the CPU core and work my way out, so let's make sure we get the AMMU mappings correct.

Brad

0 Brad Griffis over 6 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

One of our developers just gave me one other nice tip. If you're on a newer kernel such as the 4.14 branch, you should be able to run a command like this to dump the resource table at run-time:

cat /sys/kernel/debug/remoteproc/remoteproc0/resource_table > ipu1-resource-table.txt

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

ok, I will try this tomorrow and send you the results if I back in office.

Thanks
Andreas

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

yes the firmware is loading and running correctly on IPU1 and IPU2 core and I can access peripherals as well.

"Specifically, you would need to add the following mappings:

- IPU1: Unity mapping of 0x92000000 - 0x93FFFFFF
- IPU2: Unity mapping of 0x90000000 - 0x91FFFFFF"

As you can see (I hope you can verify this) in the version of ammu-decode_devm.txt I add a ammu mapping for IPU1 (Unity mapping of 0x92000000 - 0x93FFFFFF) to try to access IPU2.

Clarification:

ammu-decode_norm.txt: My base configuration before I tried to access IPU2 from IPU1
ammu-decode_devm.txt: Configuration where I try to access IPU2 from IPU1
I have only tried to access IPU2 from IPU1, the other way around I haven't tried yet cause I realized that it failed.

Regards

Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Andreas,

Thanks for clarifying on those two files. I misunderstood the first time. Sorry, it seems obvious in hindsight! I agree that you have a mapping in place for IPU1 to be able to view the IPU2 carveout space.

By the way, I think you are correct to be using devmem rather than carveout. I didn't realize that carveout is actually allocating from the CMA section (I thought it only mapped). That said, we want to allocate only once and then have the other core view that memory using devmem.

Looking at your iommu page table, it seems to me that you also have a passthrough mapping of address 0x9200000:

1: 0x92000000 0x92000002

So that said, I would expect IPU1 to be capable of reading from physical address 0x92000000 by using virtual address 0x92000000. If you run "devmem2 0x92000000" from the ARM, what do you see? I think that virtual address from IPU1 is going to look different due to the way the page tables get allocated.

Brad

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

so if you are saying that my configuration looks quite correct and should work, what else could be the root cause? Could it be some missing/outdated linux driver?
Do you have some hardware where you can cross check my or a similar configuration?

Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Andreas,

Let me elaborate with an example. You've only provided your page tables from IPU1 so let's take the example of IPU2 attempting to access the IPU1 carveout. The IPU1 carveout is at physical address 0x90000000. However, if you open a memory window on IPU1 at point to address 0x90000000 you would actually be seeing physical address 0x90200000. This can be seen in the page table dump you provided earlier. Here's the relevant entry:

1: 0x90000000 0x90200002

Your earlier test attempted to look at address 0x92000000 from both IPU1 and IPU2. You mentioned that you were seeing different data. However, I think that's the expected behavior since you were likely seeing two different addresses. I'd need to see your IPU2 page table to know for sure, but I suspect it is like this:

IPU1: Address 0x92000000 mapped to physical address 0x92000000
IPU2: Address 0x92000000 mapped to physical address 0x92200000

That's why I was asking you to verify using a different procedure. Specifically I'd like you to use the A15 running "devmem2 0x92000000" so that you can check if both IPU1 and the A15 are both seeing the same value at address 0x92000000. I suspect it is working properly right now if you check it with this method.

Brad

0 Andreas Vogt57 over 6 years ago in reply to Brad Griffis

Intellectual 730 points

Hi,

yes, you are right! I have access from IPU1 to IPU2, the addresses are mapped as you have found it out:

"1: 0x90000000 0x90200002"

I changed the devmem entry and now I can access the IPU2 firmware directly with address 0x92000000.

rsc_table of IPU1:

#define L3_IPU2_FW_DATA                   0x92000000
#define IPU1_IPU2_FW_DATA                 0x92200000
#define IPU2_FW_DATA_SIZE                 SZ_32M   

//for accessing IPU2 Firmware from IPU1
{
      TYPE_DEVMEM,
      L3_IPU2_FW_DATA, IPU1_IPU2_FW_DATA,
      IPU2_FW_DATA_SIZE, 0, 0, "IPU2_FW_ACCESS",
},

rsc_table of IPU2:

#define L3_IPU1_FW_DATA                   0x90000000
#define IPU2_IPU1_FW_DATA                 0x90200000
#define IPU1_FW_DATA_SIZE                 SZ_32M

//for accessing IPU1 Firmware from IPU2
{
      TYPE_DEVMEM,
      L3_IPU1_FW_DATA, IPU2_IPU1_FW_DATA,
      IPU1_FW_DATA_SIZE, 0, 0, "IPU1_FW_ACCESS",
},

Sorry, that I can't give you the devmem2 output but it isn't installed and it would cost me a lot of effort to integrate it in our system.

Thanks a lot for your help and for your patience

Regards,

Andreas

0 Brad Griffis over 6 years ago in reply to Andreas Vogt57

TI__Guru*** 125430 points

Andreas,

Glad to hear things are working for you now! I think it goes without saying that you will need to be very careful with this capability!

Regarding that offset between the virtual and physical address, there's a 1MB VRING sitting at the beginning of the carveout, and then there's your IPU_MEM_TEXT section (also 1MB). You can see in the IOMMU page table that you have another entry mapping address 0 to this section:

/ # cat /sys/kernel/debug/omap_iommu/58882000.mmu/pagetable
L: da: pte:
--------------------------
1: 0x00000000 0x90100002

Thanks for marking your issue as closed.

Best regards,
Brad

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