TMS320C6748: interrupt priority handling

Peter Hong

Part Number: TMS320C6748
Other Parts Discussed in Thread: SYSBIOS

Can you explain how interrupt priority works for c6748? Specifically, 1) I would assume that when maskable interrupts occur simultaneously, higher one is vectored to first. Are the remaining ones latched? 2) If a higher priority interrupt occurs while a lower one is being serviced, what happens? Is the lower one suspended?

Thanks.

Peter H.

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi Peter,

This is explained in the following documents:
1. Section 5.6.2 Nested Interrupts from TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B): www.ti.com/.../sprufe8b.pdf
I recommend reading the whole Chapter 5 Interrupts to get familiar with how the CPU handles irqs on hardware level.

2. From software RTOS kernel perspective, this is described in:
Section 3.4 Hardware Interrupts and Section 3.5 Software Interrupts from the SYSBIOS User Guide:
www.ti.com/.../spruex3u.pdf

These two documents fully answer your questions and cover all possible configurations of the IRQ & IRQ servicing.

Best Regards,
Yordan

0 Peter Hong over 7 years ago in reply to Yordan Kovachev

Intellectual 966 points

Thanks!

Peter

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TMS320C6748: interrupt priority handling