DRA72: McASP XSYNCERR unexpected frame sync with internal clocks

Eric Best

Part Number: DRA72

On the DRA72x, we are experiencing the MCASP_TXSTAT_XSYNCERR (unexpected frame sync error). In this particular case, the McASP is the master, using internal clocking for frame sync and bit clock.

Master clock is 24.576MHz (from XREF). Two serializers in TDM-8, 48KHz frame sync. WNUMEVT = 16.

What are all possible causes of this error with internal frame sync generation?

Thanks,

Eric

over 6 years ago

0 tom liu over 6 years ago

Prodigy 10 points

Add a information that the clock is from the external crystal.

0 Misael Lopez Cruz over 6 years ago in reply to tom liu

TI__Genius 9295 points

Eric,

I have not seen XSYNCERR when McASP is master for BCLK and FSYNC. It can happen when McASP is slave.

Does XSYNCERR occur randomly mid-stream? Or is it consistently reproducible? Please share the McASP register dump to take a look.

0 Eric Best over 6 years ago in reply to Misael Lopez Cruz

TI__Expert 7255 points

Hi Misa,
This item is closed. The issue has to do with improper write back of the TXSTAT register. If the XDATA bit is cleared before the XRBUF is emptied, then the XDATA bit would be set again and this could possibly create a second interrupt or EDMA event.
Regards,
Eric

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DRA72: McASP XSYNCERR unexpected frame sync with internal clocks