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AM35x Power Sequencing with time constraints

Peter Aberl
Expert 3180 points

Hello,

are there timing constraints associated with the power up and power down sequencing of the AM35x? To be more specific, are there any maximum times to be considered between the ramp of the different power domains (e.g. when VDDSHV has ramped to 3.3V the VDD_CORE shall start ramping after a 60sec delay)?

FYI, this long delay is only needed to perform functional tests at the end of the manufacturing line and won't apply to every power-up / -down sequencing during "normal" operation.

Thanks and regards,
Peter.

  • 0
    TI__Genius 16690 points

    Hello Peter,

    As long as the power up/down sequence in the data manual is followed, there is no specific timing requirements for the sequencing. Here are some comments on this from design team.

    • Once the corresponding IO voltages are stable, the pin state is defined
    • There is no need to immediately ramp up core voltage within a certain delay since pin states are defined
    • Also, no internal high leakage paths if core is not active within a certain delay of IO voltage being stable