Hi all,
I have some queries wrt to copying data in external memory on DM6437.
Lets assume we have two buffers A & B placed in external memory.
i want to copy the data in buffer A to buffer B.
i have assumed the buffer size to be in multiples of cache line size and
are aligned to cache line size and have made external memory cacheable.
i have written an assembly routine which copies 8 bytes of data every cpu cycle.
so on flat memory, to copy a buffer size of 25,600..it would require only 3,200 cycles.
but on board, i get a measurement around 73,300 cycles for the same transfer.
and i assume this is because of data cache misses. if not do let me know what could be the reason?
How could i bring this measurement closer to the flat memory case?
(should the code flow be changed or how to minimize the cache misses)
(or)
would DMA transfer yield a better performance??
Waiting for your replies,
Regards,
Sandeep