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AM5749: Understanding DDR3 Hardware leveling

Daisuke Maeda
Guru 20205 points
Part Number: AM5749

The hardware leveling execution order is as follows:

 1. Write leveling
 2. Read DQS gate training
 3. Read data eye training

Where can I find information to understand these?

Only the Write leveling seems to be defined by JEDEC DDR3 SDRAM standard (JESD79-3F).

Are there standards for the Read DQS gate and the Read data eye training?

Best regards,

Daisuke

  • 0
    TI__Guru* 86160 points
    Hi Daisuke, there is no JEDEC standard for Read gate and Read data eye training, as these are typically implemented differently by different memory controllers. There is some info on these training procedures and what they try to accomplish in the DFI DDR PHY Interface Specification (should be able to search for this on the internet).

    Regards,
    James
  • 0 in reply to JJD
    Guru 20205 points

    Hi James-san,

    Thank you for your reply.

    Does AM574x EMIF conform to the DFI DDR PHY Interface Specification, or is it implemented differently by TI?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru* 86160 points
    No, the controller to PHY interface is an implementation by TI that doesn't conform to the DFI spec. I pointed to that spec just to give a description of read gate training and read data eye training. The concepts are the same, just the implementation by various vendors will be different.

    Regards,
    James
  • 0 in reply to JJD
    Guru 20205 points

    Hi James-san,

    Thank you for your reply.

    I will check the DFI spec to understand the concepts of the gate training and data eye training.

    Best regards,

    Daisuke

  • 0 in reply to JJD
    Guru 20205 points

    Hi James-san,

    I can't understand the read trainings.

    In the JEDEC standard, the read DQS is described as being edge-aligned with the read DQ data.

    On the other hand, TRM describes as follows:

    "Read data eye training
     Through the read data eye training the delay between the rising edge of the read DQS signal and the
     rising and falling edges of the associated DQ data eye is determined. By identifying these delays, the
     midpoint between them can be calculated and thus the rising edge of the read DQS signal can be
     accurately centered within the DQ data eye.
    "

    Is the TRM description correct?

    If so, does it mean that the read DQ data is sampled on the rising edge of the read DQS signal?

    Best regards,

    Daisuke

  • 0 in reply to JJD
    Guru 20205 points

    Hi James-san,

    I have one more question for the read trainings.

    In the DFI spec, the read DQS gate can be adjusted to the approximate midpoint of the read DQS preamble prior to the DQS by the gate training.

    On the other hand, TRM describes as follows:

    "Read DQS gate training
     Read DQS Gate training is used for timing the internal read window during a read operation as opposed to
     the write leveling and read data eye training which are used for skew compensation of external signals.
     The goal of read DQS gate training is to locate the shortest delay that can be applied to each DQS gate
     such that it functions properly, then find the longest delay that can be applied to each DQS gate and keep
     its proper function again, and then align the midpoint of the DQS gate delay between these two.
    "

    Does the TRM description mean that it can be adjusted to the approximate midpoint of the read DQS preamble?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru* 86160 points

    Hi Daisuke, i've attached some slides, so hopefully some pictures can clear this up.  

    For DQS Gate training, the goal is to determine the midpoint between DQS transitions, which is when the gate should open and the controller can read the DQ data (Remember, on a read, the memory is driving both DQS and DQ, and edges are aligned). 

    Data eye training is further refining the timing, so the goal is to find the left and right edges of the valid DQ signal.  Sometimes a deskew of each bit in a byte is involved which helps open up the eye as much as possible for the whole byte.  The midpoint of the eye is the ideal time to read the data, so calculating the delays so that the controller reads at that point is the goal here.  

    training.docx

    Regards,

    james

  • 0 in reply to JJD
    Guru 20205 points

    Hi james-san,

    Thank you for your reply and helpful infomation.

    Best regards,

    Daisuke