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DRA75: Timing model creation for DRA75

Kavitha M
Prodigy 20 points
Part Number: DRA75

Hi,

We are doing signal integrity analysis for DDR3L interface with DRA75 processor in Hyperlynx. We could not able to found timing parameter details for DDR3L interface in DRA75 processor datasheet.

Could you please provide timing parameter details for DDR3L interface, it will helpful to proceed further SI analysis.

Thanks,

M.Kavitha

  • 0
    TI__Guru 54542 points
    Hello M.,

    We do not provide a traditional timing specification for the DDR3L interface. Instead, we recommend that you follow the layout guidelines from the data manual. We have performed extensive simulations and validation based on this implementation to ensure it's robust operation. The end intent is to simplify the effort on your side; and ensure first pass success.

    Regards,
    Kyle