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Problem with DMA

sandeep3378
Prodigy 140 points

 Hi all

I have tested the example DMA copy code (fastcopy) provided with DVDSK installation. Its based on EDMA3 (DMAN3 and ACPY3 modules). However, when DMA is integrated with our code. The code seems to be running into some infinite loop as soon it enters the function DMAN3_createChannels which is supposed to return the channel handle. My guess is it is something to do with either heap or stack. The document which i was referring to was spraag1.pdf. It also gives the example code (fastcopy).

 

Waiting for your replies,

Regards,

Sandeep

  • TI__Mastermind 41665 points

    The DMAN3_createChannels function should always return with something, even if it is an error code. It is possible that running out of stack space could cause a crash, so it may be worth increasing your stack to see if it changes the failure pattern, however the heap should not have it locking up like this, if you were out of heap it should return DMAN3_EOUTOFMEMORY. One thought on this from a BIOS standpoint, I would be curious what context you are calling this function in (main, TSK, SWI, HWI, etc.), though the documentation lists no limitations on this, the fastcopy example is calling the function from main as opposed to after main when the BIOS scheduler starts (i.e. TSKs).

  • in reply to Bernie Thompson TI
    Prodigy 40 points

     Hi all,

    I am working on DM6437 platform and have few queries on DMA usage.

    I am using DMAN3 and ACPY3 interface in my application with QDMA channels.

    1. DMA Speed

    * What is the speed at which DMA operates relative to cpu?

    * Does the method of profiling the cycles between ACPY3_start and end of ACPY3_wait give an idea about the time

      consumed in DMA transfer. If not, Is there a way to measure it.

    2. DMA prioritiy

    * Do transfers happen in parallel if the priorities of the transfer requests are different?

     Say requests T0 is of low and T1 of high priority. If both are scheduled just one after the other.

     Do the transfers happen simultaneously as there are multiple queues and TCs based on priority.

     

    Thanks,

    Regards,

    John 

  • in reply to John3588
    TI__Guru*** 125430 points

    John,

    In the future please start a new post rather than replying to someone else's.

    John said:

     Hi all,

    I am working on DM6437 platform and have few queries on DMA usage.

    I am using DMAN3 and ACPY3 interface in my application with QDMA channels.

    1. DMA Speed

    * What is the speed at which DMA operates relative to cpu?

    * Does the method of profiling the cycles between ACPY3_start and end of ACPY3_wait give an idea about the time

      consumed in DMA transfer. If not, Is there a way to measure it.

    The EDMA3 controller operates at CPU/3.

    Yes, I suppose measuring that measurement would give you an indication of the transfer time. 

    Make sure you're not just calling ACPY3_start followed immediately by ACPY3_wait.  That is, try and do as much "other stuff" as possible before you wait for the DMA transfer to complete.

    John said:

    2. DMA prioritiy

    * Do transfers happen in parallel if the priorities of the transfer requests are different?

     Say requests T0 is of low and T1 of high priority. If both are scheduled just one after the other.

     Do the transfers happen simultaneously as there are multiple queues and TCs based on priority.

     

    Maybe someone else can comment on the implementation of ACPY.  From a hardware perspective the various TCs are capable of simultaneous transfer as long as there are no port conflicts.  So if ACPY allows you to use multiple queues then you would have simultaneous transfers.

    Brad

  • in reply to Brad Griffis
    Prodigy 40 points

    Hi Brad,

    Thanks for the reply..Surely i will start a new post next time.

    Regards,

    John