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AM6548: ICSSG UART max speed

HS FAE Germany
Mastermind 32890 points

Part Number: AM6548
Other Parts Discussed in Thread: AM4376

Hello,
what would be the max speed of the ICSS UART. Customer ask for a 48MBit baudrate.

Regards, Holger

  • 0
    TI__Genius 16030 points
    Hi Holger,

    The max speed of the UART inside of PRU_ICSSG is 12Mbps.

    Regards,
    Melissa
  • 0 in reply to melissaw
    TI__Mastermind 32890 points

    Melissa,
    what serial interface do we have on the AM65xx with such a speed to connect to a FPGA? LVDS?

    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Genius 16030 points
    Hi Holger,

    Below are a few peripherals you could look at:

    MCSPI (48MHz max)
    MCASP
    OSPI (which supports SPI, quad-SPI, and octal-SPI protocols)

    Regards,
    Melissa
  • 0 in reply to melissaw
    TI__Mastermind 32890 points

    Hello Melissa,
    customer is more interesting in the AM4376 now. Is the MCSPI speed the same?

    What would be the max speed of the soft-UART on the PRU?
    What is the speed of the PRU SPI?
    What is the speed of the shift out?

    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Genius 16030 points
    Hi Holger,

    The max McSPI speed is still 48MHz. However, please note that the achievable speed depends on the device’s OPP setting, loading, and McSPI mode. More details can be found in the “Timing and Switching Characteristics” section of the device datasheet.

    The max baudrate of the PRU soft-UART is 115200.
    A PRU SPI implementation would be slower than the hardware McSPI mentioned above.
    The speed of shift out is going to be limited by the amount of PRU processing required for a given application.

    Regards,
    Melissa
  • 0 in reply to melissaw
    TI__Mastermind 32890 points

    Hello Melissa,

    > The speed of shift out is going to be limited by the amount of PRU processing required for a given application.
    ok. What is the speed the data would be on clocked on the out pin?

    Btw, the 48Mbit/s baudrate of the MCSPI is per channel, right?


    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Genius 16030 points
    Holger,

    Question #1:
    As mentioned in the timing section of the device datasheet, the shift out clock can operate at a max of 100 MHz, but the amount of PRU processing required by your application may limit what speed you can realistically achieve. Note that the PRU-ICSS’s shift out clock is controlled by two cascaded dividers, so the PRU firmware can adjust the speed to whenever rate the application can keep up with and avoid underruna.

    This “Designing a PRU Application” training outlines the basic conspectus and considerations for estimating the number of PRU cycles required by an application and assessing what clock speed is feasible-- training.ti.com/sitara-processors-building-blocks-for-pru-development-appdesign

    Question #2:
    Correct, 48MHz is per channel when operating with a "low load". See section 5.13.13.1.2 (McSPI-- Master Mode) in the “Timing and Switching Characteristics” section of the device datasheet.

    Regards,
    Melissa