C55xx - PLL stays in Bypass mode and never locks

Hello Nelson,

Please refer to the PLL config section and other reference material in the CSL API Reference Guide for details. Let us know if you still have questions. 

Thanks,

Mugdha

Hello Mugdha, thank you for your reply.

I have read the API Reference Guide and I am using the following functions to setup the PLL:

PLL_Config myConfig = {

   0,    //IAI

   1,    //IOB

   1,    //PLL multiply value; 

   1   //Divide by

    };

PLL_config(&myConfig);

and

PLL_setFreq(1,1);

When multiply value is 1, the program is ok. But when the multiply value is more than 1, the system stays looping between these assembly instructions:

BTST #0,port(*AR3),TC1

BCC #0x023dcd,!TC1

Debugging the USB Example, the same problem occurred in this function:

while(!ReadMask(pCMOD -> clkmd, CLKMD_LOCK));

I believe that it is waiting for the LOCK flag bit to go to 1 but it never does.

So, what can I be doing wrong? have I missed some configuration of the simulator or the debugger?

Hi!

I am trying now to program a TMS320VC5507 hardware, since it is very similar to C5509. I used the CSL Macros to configure PLL. In my code, shown below, I have set "mul" to increase from 1 to 5 and "div" to have the constant value 1, which means that the PLL output is the clock input divided by 2. The clock rate goes up accordingly until mul = 3. Although, when mul = 4 the system halts in the instruction PLL_FSET(CLKMD, PLLENABLE, 1);

Also, when I measure CLKOUT pin, with the external crystal oscillator having frequency 12MHz, I get only 3.999MHz , then 12MHz then 8MHz then the system halts. What can be going wrong? Is there a software protection for configuring the PLL? Can in be constantly reconfigured?

#define CLMKD_LOCK 0x0001

//Disable PLL

PLL_FSET(CLKMD, PLLENABLE, 0);

delay(1000);

//Set PLL Multiply

PLL_FSET(CLKMD, PLLMULT, mul);

PLL_FSET(CLKMD, PLLDIV, div);

delay(1000);

//Enable PLL

PLL_FSET(CLKMD, PLLENABLE, 1);

delay(1000);

do{

//LOCK

lock_flag = (PLL_RGET(CLKMD) & CLKMD_LOCK); //ReadMask

timeout++;

}while((lock_flag==0)&&(timeout<20));

Hi!

I believe my mistake was to try to configure PLL to Bypass mode and only then to lock mode.

What I made was first set the CLKOUT pin to be divided by 14, placing 7 in the SYSR CLKDIV register, and then configure the PLL frequency directly to the clock I wanted, without going to Bypass mode.

Thank you very much!

Nelson