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CCS/AM3359: Configuration of DDR3 on custom board

Part Number: AM3359

Tool/software: Code Composer Studio

Hi,

I am using a customized board with AM3359 , DDR3 Chip (MT41J128M16JT-125) based on the Sitara ICE v2 and are operating the DDR3 at 400 MHz operating speed .

I have attached the Customized GEL file along with the DDR3 Register calculation sheet, DDR3 Phy Calculation scheet.

I am following the instructions from the wiki: http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

But the S/W leveling only reports zeros:

Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0x0

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
0x40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
0x74

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x0

***************************************************************
    The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE    
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0

Optimal values have been found!!

***************************************************************
    The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE    
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
***************************************************************

===== END OF TEST =====

I also use the GEL scripts ,the test of DDR_DataTransferCheck() and EDMA() to test the DDR both of which is failed The result is also in a log file attached.

Kindly help in configuring the DDR.

Thanks in advance,

ChinmayGEL file used.zip