Can the DM647 PCI interface be a host?

It looks like the DM6467T has PCI Host capability, BUT this part shares pins between PCI and EMIF busses. Is there something that has separate PCI and EMIF busses and can act as a PCI host?

Tom,

Yes, the DM647 PCI peripheral can act as a PCI bus master, according to the DM647 datasheet.

Regards,

Brad

Does PCI bus master equate to a PCI - Host??

-Tom-

Tom,

You are correct.  Being a PCI Host encompasses more than just being a PCI bus master.  SPRU581 describes how the DSP can be a PCI host, along with several limitations.  I've reproduced the applicable text from that document below.

Regards,

Brad

8.3 DSP as System Host

-IDSELs must be under DSP control.

-There is just one PCI bus segment, that is, the DSP cannot generate type 1 configuration cycles.

-External logic to arbitrate the bus.

Tom,

It turns out that these instructions have to be updated in a few places in order to apply to the DM647.  We'll post the requried changes to the above procedure ASAP.

Thanks,

Brad

Brad,

Thanks, PLEASE post the info on the DM647 because it looks as though that will be targeted.

-Tom-

Tom,

Here is the text, updated for DM648/7.

Regards,

Brad

8.3 DSP as System Host

The PCI port can perform master configuration cycles regardless of the master

bit setting in the PCI configuration registers. Also, the internal slave and master

can run concurrently, allowing the DSP to read and write its own configuration

registers over the PCI bus. These capabilities allow the PCI port to act as a

system host by configuring itself and the rest of the PCI bus. This is subject

to the following limitations:

_ IDSELs must be under DSP control.

_ There is just one PCI bus segment, that is, the DSP cannot generate

type 1 configuration cycles.

_ External logic to arbitrate the bus.

8.3.1 Generating IDSEL

To properly configure the bus, the DSP must be able to assert the IDSEL line

of each device at the appropriate time. The PCI interface does not directly

provide for this; it must be accomplished by indirect means. The following

sections provide two different procedures to generate IDSEL.

8.3.1.1 Resistively Coupled IDSEL

Resistively coupling IDSEL is a common and easy method of generating

IDSELs; however, you must be careful to adhere to PCI specification with this

method. Using coupled IDSELs requires the host to step the address phase

onto the bus to allow IDSEL sufficient time to propagate to the target device.

The PCI interface does not do address stepping. The compact nature of most

systems where the DSP is the host should allow for a functional coupling

without address stepping. Regardless, it is your responsibility to ensure the

IDSEL signal propagates through the resistive coupling in time to meet PCI’s

timing specification.

When using resistive coupling for IDSEL generation, the procedure to read or

write a configuration word is as follows:

1) For writes, load the data value in PCIMCFGDAT. For reads, skip this step.

2) Set PCIMCFGADR:

a) PCIMCFGADR [31−11] = one bit set to select appropriate device’s IDSEL

(important: only one bit should be set at a time)

b) PCIMCFGADR [10−8] = device function to be addressed

c) PCIMCFGADR [7−0] = 32-bit configuration word address (See PCI

specification for type 0 configuration access details)

3) Use PCIMCFGCMD to initiate a single read/write configuration access.

4) Poll for READY==1 to ensure the configuration access is complete

5) For reads, read the received data from PCIMCFGDAT.

8.3.1.2 GPIO Generated IDSEL

An alternate and fully-compliant method of generating IDSEL is to attach the

IDSEL lines to GPIO pins and control them directly. The procedure is only

slightly different from above:

1) Set GPIO to enable one IDSEL only (important: only one IDSEL should be

enabled at a time) You should read back new values written to GPIO pins

to avoid race conditions.

2) For writes, load the data value in PCIMCFGDAT. For reads, skip this step.

3) Set PCIMA:

a) PCIMCFGADR[11−8] = device function to be addressed

b) PCIMCFGADR [7−0] = 32-bit configuration word address (See PCI

specification for type 0 configuration access details)

4) Use PCIMCFGCMD to initiate a single read/write configuration access.

5) Poll for READY==1 to ensure the configuration access is complete

6) For reads, read the received data from PCIMCFGDAT.

7) Set GPIO to turn off IDSEL