Linux: DRA750 MLO halt mmc_init

user1897841

Other Parts Discussed in Thread: DRA756, DRA750, CSD

Tool/software: Linux

Hi，

The 4G emmc is initialized in the mlo of the DRA750. The result is halt in the mmc_init function. The DRA756 can initialize the eMMC normally. What is the difference between the DRA750 and the DRA756?

Look forward to your reply.Thanks.

over 6 years ago

0 Vishal Mahaveer over 6 years ago

TI__Mastermind 33360 points

Hi,

There is no eMMC difference between DRA750 and DRA756.

Regards,
Vishal

0 Vishal Mahaveer over 6 years ago in reply to Vishal Mahaveer

TI__Mastermind 33360 points

You can see the difference between DRA750 and DRA756 here
www.ti.com/.../DRA75

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

I see that the memory on the chip is different. Is this problem related to on-chip memory?

0 Vishal Mahaveer over 6 years ago in reply to user1897841

TI__Mastermind 33360 points

mmc operation has no dependency on on-chip memory.

Other than the processors being different what else is different between these 2 boards?
Do both the boards (DRA750 board and DRA756 board) have exactly same board design.

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

dra750 and dra756 on a same board.

0 Vishal Mahaveer over 6 years ago in reply to user1897841

TI__Mastermind 33360 points

Could you share the boot logs?

Also could you put more prints in mmc_init function and drivers/mmc/omap_hsmmc.c to see where it's stuck. You could also try adding '#define DEBUG' on top of these files to get debug logs.

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

Hi ,

Log as follows:

static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)

{
struct hsmmc *mmc_base;
unsigned int flags, mmc_stat;
ulong start;
#ifdef SUPPORTS_ADMA
struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
priv->last_cmd = cmd->cmdidx;
#endif

mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
printf("cheng, %s 1\n", __func__);

if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;

start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting on cmd inhibit to clear\n",
__func__);

return TIMEOUT;
}

printf("cheng, %s 2\n", __func__);
}
writel(0xFFFFFFFF, &mmc_base->stat);
start = get_timer(0);
while (readl(&mmc_base->stat)) {

printf("cheng, %s 3\n", __func__);
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for STAT (%x) to clear\n",
__func__, readl(&mmc_base->stat));
return TIMEOUT;
}
}
/*
* CMDREG
* CMDIDX[13:8] : Command index
* DATAPRNT[5] : Data Present Select
* ENCMDIDX[4] : Command Index Check Enable
* ENCMDCRC[3] : Command CRC Check Enable
* RSPTYP[1:0]
* 00 = No Response
* 01 = Length 136
* 10 = Length 48
* 11 = Length 48 Check busy after response
*/
/* Delay added before checking the status of frq change
* retry not supported by mmc.c(core file)
*/
if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
udelay(50000); /* wait 50 ms */

if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = 0;
else if (cmd->resp_type & MMC_RSP_136)
flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
else if (cmd->resp_type & MMC_RSP_BUSY)
flags = RSP_TYPE_LGHT48B;
else
flags = RSP_TYPE_LGHT48;

/* enable default flags */
flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
MSBS_SGLEBLK);
flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);

if (cmd->resp_type & MMC_RSP_CRC)
flags |= CCCE_CHECK;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= CICE_CHECK;

if (data) {
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
data->blocksize = 512;
writel(data->blocksize | (data->blocks << 16),
&mmc_base->blk);
} else
writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

if (data->flags & MMC_DATA_READ)
flags |= (DP_DATA | DDIR_READ);
else
flags |= (DP_DATA | DDIR_WRITE);

#ifdef SUPPORTS_ADMA
if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) {
omap_hsmmc_prepare_data(mmc, data);
flags |= DE_ENABLE;
}
#endif
}

mmc_enable_irq(mmc, cmd);

writel(cmd->cmdarg, &mmc_base->arg);
udelay(20); /* To fix "No status update" error on eMMC */
writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return TIMEOUT;
}

printf("cheng, %s 4\n", __func__);
} while (!mmc_stat);

if ((mmc_stat & IE_CTO) != 0) {
mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
return TIMEOUT;
} else if ((mmc_stat & ERRI_MASK) != 0)
return -1;

printf("cheng, %s 5\n", __func__);

if (mmc_stat & CC_MASK) {
writel(CC_MASK, &mmc_base->stat);
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (cmd->resp_type & MMC_RSP_136) {
/* response type 2 */
cmd->response[3] = readl(&mmc_base->rsp10);
cmd->response[2] = readl(&mmc_base->rsp32);
cmd->response[1] = readl(&mmc_base->rsp54);
cmd->response[0] = readl(&mmc_base->rsp76);
} else
/* response types 1, 1b, 3, 4, 5, 6 */
cmd->response[0] = readl(&mmc_base->rsp10);
}
}

#ifdef SUPPORTS_ADMA
if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) {
if (mmc_stat & IE_ADMAE) {
omap_hsmmc_dma_cleanup(mmc);

printf("cheng, %s 5\n", __func__);
return -1;
}

do {
mmc_stat = readl(&mmc_base->stat);
if (mmc_stat & TC_MASK) {
writel(readl(&mmc_base->stat) | TC_MASK,
&mmc_base->stat);
break;
}

printf("cheng, %s 6\n", __func__); //here mmc_stat=0x0

} while (1);

omap_hsmmc_dma_cleanup(mmc);
return 0;
}
#endif

if (data && (data->flags & MMC_DATA_READ)) {
mmc_read_data(mmc_base, data->dest,
data->blocksize * data->blocks);
} else if (data && (data->flags & MMC_DATA_WRITE)) {
mmc_write_data(mmc_base, data->src,
data->blocksize * data->blocks);
}

printf("cheng, %s 7\n", __func__);
return 0;
}

[BEGIN] 2018/12/6 9:43:10
U-Boot#
U-Boot SPL 2016.05-svn23831 (Dec 06 2018 - 09:42:12)
spl_boot_list[0] = a
spl: loading remote core image dra7-dsp2-fw.xe66
no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v
cheng, emmc init

CMD_SEND:0
ARG 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_NONE
CMD_SEND:8
ARG 0x000001AA
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
RET -19
CMD_SEND:55
ARG 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
RET -19
CMD_SEND:0
ARG 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_NONE
CMD_SEND:1
ARG 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R3,4 0x00FF8080
CMD_SEND:1
ARG 0x40300080
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R3,4 0x00FF8080
CMD_SEND:1
ARG 0x40300080
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R3,4 0xC0FF8080
cheng, mmc_complete_init 1
cheng, mmc_startup 1
CMD_SEND:2
ARG 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R2 0xFE014E4D
0x4D433034
0x47106013
0x788424F5

DUMPING DATA
000 - FE 01 4E 4D
004 - 4D 43 30 34
008 - 47 10 60 13
012 - 78 84 24 F5
cheng, mmc_startup 2
CMD_SEND:3
ARG 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R1,5,6,7 0x00000500
cheng, mmc_startup 3
CMD_SEND:9
ARG 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R2 0xD06E0132
0x0F5913FF
0xFFFFFFE7
0x92400041

DUMPING DATA
000 - D0 6E 01 32
004 - 0F 59 13 FF
008 - FF FF FF E7
012 - 92 40 00 41
CMD_SEND:13
ARG 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R1,5,6,7 0x00000700
cheng, mmc_startup 4
CMD_SEND:7
ARG 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
MMC_RSP_R1,5,6,7 0x00000700
cheng, mmc_startup 5
cheng, mmc_send_ext_csd
CMD_SEND:8
ARG 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6
cheng, omap_hsmmc_send_cmd 6

0 Peter Li79 over 6 years ago in reply to user1897841

TI__Expert 8940 points

CTT-DRA75x_DRA74x_SR2.0_SR1.1-REG_DUMP.gelHi, Wen:

As what we just discussed, in normal condition (DRA756), the mmc clock is about 24MHz, but now it is about 40kHz.

Please dump the register (refer to the inserted .gel script) and we can check the clock setting.

Please dump one working configuration as well.

0 user1897841 over 6 years ago in reply to user1897841

Intellectual 420 points

Hi,
In the MLO of the dra750, the emmc clk I measured is 400k, and in the MLO of dra756 the emmc clk is 24M.

0 user1897841 over 6 years ago in reply to Peter Li79

Intellectual 420 points

Fullscreen dra750.log Download

[BEGIN] 2018/12/6 14:59:24
U-Boot#      
U-Boot SPL 2016.05-svn23831 (Dec 06 2018 - 14:57:52)
spl_boot_list[0] = a
no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v


4a005560 30000
4ae06118 0
4a008920 70000
4ae06190 0
4a0052e4 0
4ae061c8 0
4ae06174 0
4a009848 2
4ae07888 30000
4a005228 208
4a002360 0
4a0051ec 800000
4a009770 101
4a009908 30000
4a005254 0
4ae06154 0
4a009858 2
4a00521c 10a04
4ae061bc 0
4a009750 30000
4a009780 1
4a0097a8 30000
4a008778 30000
4a009328 1040002
4a005234 5
4a005244 1
4a0052b8 204
4a009388 70000
4a005130 2
4a005154 5
4a0098e8 30000
4a008e40 30000
4a005550 30000
4a0093e8 30000
4ae07830 2
4a00516c 81f409
4a009620 30000
4ae06134 0
4a005520 70000
4a005580 30000
4a008210 1
4a008e28 30000
4ae061a0 0
4a009738 2
4a005248 1
4a009800 30000
4a0052d8 5
4a005140 3e
4a0052e8 1
4a0098a8 30000
4a009350 70000
4ae06180 0
4a009798 30000
4ae061c0 0
4a0051e0 5
4a008c00 30000
4ae06108 0
4a0051f0 1
4ae07840 1000002
4ae06170 0
4a0097d8 30000
4a005210 7
4a0098f0 30000
4ae07838 1
4a005220 202
4a009868 30000
4a008158 3
4a00519c 0
4a0086a0 0
4ae061d4 0
4ae06138 0
4ae061c4 0
4a0051f4 1
4ae06114 0
4a008e50 2000001
4a009760 1
4ae061d0 0
4a009878 30000
4a00814c 6004
4a008200 5
4a005160 7
4a0093b0 70000
4a005170 201
4ae061d8 0
4a009120 70000
4a008b30 1
4a0052c0 228
4a0051ac 0
4ae061a8 0
4a00815c 4
4a005568 30000
4a0093d0 8000002
4a009820 30000
4a009220 70000
4a002534 6000000
4a009020 70000
4a0098d0 30000
4a0093e0 30000
4a009130 70000
4a009850 2
4a005158 4
4a005764 70000
4a009788 30000
4a008160 20a
4ae07878 30000
4a009030 70000
4a005744 30000
4a009890 30000
4a009870 30000
4a0097f0 30000
4ae06194 0
4a009340 70000
4a0097c4 30000
4a009810 1
4a0097b0 30000
4a0051dc 0
4a008780 30000
4a005144 5
4a008164 2
4a008140 7
4a0097c8 30000
4a008150 804
4ae0610c 0
4a0098c8 30000
4ae06130 0
4ae06198 0
4ae06168 0
4ae06184 0
4ae06148 0
4a0051a0 5
4a0051b0 1
4ae0619c 0
4a0056a0 70000
4a009740 30000
4a00821c 0
4a009808 30000
4a009728 30000
4a005290 0
4ae061cc 0
4a005558 30000
4ae0612c 0
4ae06178 0
4a005620 70000
4a009830 30000
4a00818c 4000000
4a00820c 4000000
4a008f28 30000
4a002544 f757fdc0
4a009898 30000
4ae061b0 0
4a009840 2
4a009768 1
4a009904 30000
4a00515c 6
4ae061b8 0
4a0093b8 70000
4a008b38 1
4ae061b4 0
4a009778 1
4a005570 30000
4a0097a0 2
4a0052a4 0
4a005660 70000
4ae06110 2
4a009828 30000
4ae06164 0
4a008b40 0
4ae06160 0
4ae0615c 0
4ae06158 0
4a009028 70000
4a0098e0 30000
4a005284 5
4a005294 1
4a009330 1040002
4a009358 70000
4ae0614c 0
4a005420 70000
4a0093f0 70000
4ae06150 0
4a008180 5
4a0052b4 fa04
4a008190 1
4a00512c 10a04
4a005100 110
4a0097f8 30000
4a008f20 70000
4ae0618c 0
4a0098a0 30000
4a009348 70000
4ae061e0 0
4a0098c0 30000
4a009790 30000
4a009838 1000002
4a0098b8 30000
4a009818 1
4a0097b8 30000
4a008728 1
4a0097d0 30000
4a008e20 1
4a0098f8 30000
4ae07880 30000
4ae0616c 0
4a009860 30000
4ae061ac 0
4a0098b0 30000
4a0052c4 208
4a00513c 204
4ae06120 0
4a009748 30000
4ae06144 0
4a005578 30000
4a005240 0
4a009730 30000
4a0052a8 7
4a005120 7
4a0086b0 0
4ae06188 0
4ae061a4 0
4ae06128 0
cheng, emmc init

CMD_SEND:0
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_NONE
CMD_SEND:8
		ARG			 0x000001AA
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
		RET			 -19
CMD_SEND:55
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
		RET			 -19
CMD_SEND:0
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_NONE
CMD_SEND:1
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R3,4		 0x00FF8080 
CMD_SEND:1
		ARG			 0x40300080
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R3,4		 0x00FF8080 
CMD_SEND:1
		ARG			 0x40300080
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R3,4		 0xC0FF8080 
cheng, mmc_complete_init 1
cheng, mmc_startup 1
CMD_SEND:2
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R2		 0xFE014E4D 
		          		 0x4D433034 
		          		 0x47106013 
		          		 0x788424F5 

					DUMPING DATA
					000 - FE 01 4E 4D 
					004 - 4D 43 30 34 
					008 - 47 10 60 13 
					012 - 78 84 24 F5 
cheng, mmc_startup 2
CMD_SEND:3
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000500 
cheng, mmc_startup 3
CMD_SEND:9
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R2		 0xD06E0132 
		          		 0x0F5913FF 
		          		 0xFFFFFFE7 
		          		 0x92400041 

					DUMPING DATA
					000 - D0 6E 01 32 
					004 - 0F 59 13 FF 
					008 - FF FF FF E7 
					012 - 92 40 00 41 
CMD_SEND:13
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000700 
cheng, mmc_startup 4
CMD_SEND:7
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000700 
cheng, mmc_startup 5
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0

Fullscreen dra756.log Download

[BEGIN] 2018/12/6 15:03:38

U-Boot SPL 2016.05-svn23831 (Dec 06 2018 - 14:57:52)
spl_boot_list[0] = a
no pinctrl for ddr_1_8v
4a005560 30000
4ae06118 0
4a008920 70000
4ae06190 0
4a0052e4 0
4ae061c8 0
4ae06174 0
4a009848 2
4ae07888 30000
4a005228 208
4a002360 0
4a0051ec 800000
4a009770 101
4a009908 30000
4a005254 0
4ae06154 0
4a009858 2
4a00521c 10a04
4ae061bc 0
4a009750 30000
4a009780 1
4a0097a8 30000
4a008778 30000
4a009328 1040002
4a005234 5
4a005244 1
4a0052b8 204
4a009388 70000
4a005130 2
4a005154 5
4a0098e8 30000
4a008e40 30000
4a005550 30000
4a0093e8 30000
4ae07830 2
4a00516c 81f409
4a009620 30000
4ae06134 0
4a005520 70000
4a005580 30000
4a008210 1
4a008e28 30000
4ae061a0 0
4a009738 2
4a005248 1
4a009800 30000
4a0052d8 5
4a005140 3e
4a0052e8 1
4a0098a8 30000
4a009350 70000
4ae06180 0
4a009798 30000
4ae061c0 0
4a0051e0 5
4a008c00 30000
4ae06108 0
4a0051f0 1
4ae07840 1000002
4ae06170 0
4a0097d8 30000
4a005210 7
4a0098f0 30000
4ae07838 1
4a005220 202
4a009868 30000
4a008158 3
4a00519c 0
4a0086a0 0
4ae061d4 0
4ae06138 0
4ae061c4 0
4a0051f4 1
4ae06114 0
4a008e50 2000001
4a009760 1
4ae061d0 0
4a009878 30000
4a00814c 6004
4a008200 5
4a005160 7
4a0093b0 70000
4a005170 201
4ae061d8 0
4a009120 70000
4a008b30 1
4a0052c0 228
4a0051ac 0
4ae061a8 0
4a00815c 4
4a005568 30000
4a0093d0 8000002
4a009820 30000
4a009220 70000
4a002534 0
4a009020 70000
4a0098d0 30000
4a0093e0 30000
4a009130 70000
4a009850 2
4a005158 4
4a005764 70000
4a009788 30000
4a008160 20a
4ae07878 30000
4a009030 70000
4a005744 30000
4a009890 30000
4a009870 30000
4a0097f0 30000
4ae06194 0
4a009340 70000
4a0097c4 30000
4a009810 1
4a0097b0 30000
4a0051dc 0
4a008780 30000
4a005144 5
4a008164 2
4a008140 7
4a0097c8 30000
4a008150 804
4ae0610c 0
4a0098c8 30000
4ae06130 0
4ae06198 0
4ae06168 0
4ae06184 0
4ae06148 0
4a0051a0 5
4a0051b0 1
4ae0619c 0
4a0056a0 70000
4a009740 30000
4a00821c 0
4a009808 30000
4a009728 30000
4a005290 0
4ae061cc 0
4a005558 30000
4ae0612c 0
4ae06178 0
4a005620 70000
4a009830 30000
4a00818c 4000000
4a00820c 4000000
4a008f28 30000
4a002544 f757fdc0
4a009898 30000
4ae061b0 0
4a009840 2
4a009768 1
4a009904 30000
4a00515c 6
4ae061b8 0
4a0093b8 70000
4a008b38 1
4ae061b4 0
4a009778 1
4a005570 30000
4a0097a0 2
4a0052a4 0
4a005660 70000
4ae06110 2
4a009828 30000
4ae06164 0
4a008b40 0
4ae06160 0
4ae0615c 0
4ae06158 0
4a009028 70000
4a0098e0 30000
4a005284 5
4a005294 1
4a009330 1040002
4a009358 70000
4ae0614c 0
4a005420 70000
4a0093f0 70000
4ae06150 0
4a008180 5
4a0052b4 fa04
4a008190 1
4a00512c 10a04
4a005100 110
4a0097f8 30000
4a008f20 70000
4ae0618c 0
4a0098a0 30000
4a009348 70000
4ae061e0 0
4a0098c0 30000
4a009790 30000
4a009838 1000002
4a0098b8 30000
4a009818 1
4a0097b8 30000
4a008728 1
4a0097d0 30000
4a008e20 1
4a0098f8 30000
4ae07880 30000
4ae0616c 0
4a009860 30000
4ae061ac 0
4a0098b0 30000
4a0052c4 208
4a00513c 204
4ae06120 0
4a009748 30000
4ae06144 0
4a005578 30000
4a005240 0
4a009730 30000
4a0052a8 7
4a005120 7
4a0086b0 0
4ae06188 0
4ae061a4 0
4ae06128 0
cheng, emmc init

CMD_SEND:0
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_NONE
CMD_SEND:8
		ARG			 0x000001AA
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
		RET			 -19
CMD_SEND:55
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
		RET			 -19
CMD_SEND:0
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_NONE
CMD_SEND:1
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R3,4		 0x00FF8080 
CMD_SEND:1
		ARG			 0x40300080
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R3,4		 0x00FF8080 
CMD_SEND:1
		ARG			 0x40300080
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R3,4		 0xC0FF8080 
cheng, mmc_complete_init 1
cheng, mmc_startup 1
CMD_SEND:2
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R2		 0xFE014E4D 
		          		 0x4D433034 
		          		 0x47101013 
		          		 0x78842487 

					DUMPING DATA
					000 - FE 01 4E 4D 
					004 - 4D 43 30 34 
					008 - 47 10 10 13 
					012 - 78 84 24 87 
cheng, mmc_startup 2
CMD_SEND:3
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000500 
cheng, mmc_startup 3
CMD_SEND:9
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R2		 0xD06E0132 
		          		 0x0F5913FF 
		          		 0xFFFFFFE7 
		          		 0x92400041 

					DUMPING DATA
					000 - D0 6E 01 32 
					004 - 0F 59 13 FF 
					008 - FF FF FF E7 
					012 - 92 40 00 41 
CMD_SEND:13
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000700 
cheng, mmc_startup 4
CMD_SEND:7
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000700 
cheng, mmc_startup 5
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
cheng, mmc_startup 5.1
cheng, mmc_startup 5.2
cheng, mmc_startup 5.3
cheng, mmc_startup 5.4
cheng, mmc_startup 6
cheng, mmc_startup 7
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
CMD_SEND:6
		ARG			 0x03B90100
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1b		 0x00000800 
CMD_SEND:13
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
cheng, mmc_startup 8
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
CMD_SEND:6
		ARG			 0x03B70100
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1b		 0x00000800 
CMD_SEND:13
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
CMD_SEND:6
		ARG			 0x03B70500
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1b		 0x00000800 
CMD_SEND:13
		ARG			 0x00010000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd 
CMD_SEND:8
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
		MMC_RSP_R1,5,6,7 	 0x00000900 
cheng, mmc_send_ext_csd , err=0
cheng, mmc_startup 9
CMD_SEND:17
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
		MMC_RSP_R1,5,6,7 	 0x00000900 
CMD_SEND:17
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
		MMC_RSP_R1,5,6,7 	 0x00000900 
mmc_init: 0, time 605 (retries 0)
Foot at common/spl/spl_mmc.c:978/spl_mmc_load_core()
Core = dra7-dsp2-fw.xe66 at 0xaa800000, start = 0x6800, size = 0x1000
CMD_SEND:18
		ARG			 0x00006800
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
		MMC_RSP_R1,5,6,7 	 0x00000900 
CMD_SEND:12
		ARG			 0x00000000
cheng, omap_hsmmc_send_cmd 1
		MMC_RSP_R1b		 0x00000900 
Foot at common/spl/spl_mmc.c:1022/spl_mmc_load_core()
ELF: 0xffffffff 0xffffffff
## No elf image at address 0xaa800000
Error loading remotecore DSP2!,Continuing with boot ...
Foot at common/spl/spl.c:291/spl_load_image()

[END] 2018/12/6 15:03:47

Hi,Peter:

Log as follow:

0 Peter Li79 over 6 years ago in reply to user1897841

TI__Expert 8940 points

Hi, Wen:

As what we discussed, in the log file, it seems the clock tree configuration is same.
For next step, let's check the differences in the MMC2 registers.

0 user1897841 over 6 years ago in reply to Peter Li79

Intellectual 420 points

Hi, Peter:

mmc2 regs log as follow:

dra750_mmc.log

Fullscreen dra756_mmc2.log Download

[BEGIN] 2018/12/6 16:15:35
=> 
U-Boot SPL 2016.05-svn23831 (Dec 06 2018 - 16:09:23)
spl_boot_list[0] = a
cpu_id[0x4037dc00]=0x7520110 no pinctrl for ddr_1_8v
cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 cpu_id[0x4037dc00]=0x7520110 CPU  : cpu_id[0x4037dc00]=0x7520110 DRA752-GP ES1.1
mmc reg start:



480b4000 40200303
480b4004 4b
480b4008 0
480b400c 0
480b4010 28
480b4014 0
480b4018 0
480b401c 0
480b4020 0
480b4024 0
480b4028 0
480b402c 0
480b4030 0
480b4034 0
480b4038 0
480b403c 0
480b4040 0
480b4044 0
480b4048 0
480b404c 0
480b4050 0
480b4054 0
480b4058 0
480b405c 0
480b4060 0
480b4064 0
480b4068 0
480b406c 0
480b4070 0
480b4074 0
480b4078 0
480b407c 0
480b4080 0
480b4084 0
480b4088 0
480b408c 0
480b4090 0
480b4094 0
480b4098 0
480b409c 0
480b40a0 0
480b40a4 0
480b40a8 0
480b40ac 0
480b40b0 0
480b40b4 0
480b40b8 0
480b40bc 0
480b40c0 0
480b40c4 0
480b40c8 0
480b40cc 0
480b40d0 0
480b40d4 0
480b40d8 0
480b40dc 0
480b40e0 0
480b40e4 0
480b40e8 0
480b40ec 0
480b40f0 0
480b40f4 0
480b40f8 0
480b40fc 0
480b4100 0
480b4104 0
480b4108 0
480b410c 0
480b4110 2015
480b4114 1
480b4118 0
480b411c 0
480b4120 0
480b4124 0
480b4128 8000
480b412c 600
480b4130 0
480b4134 80000000
480b4138 0
480b413c 0
480b4140 0
480b4144 0
480b4148 0
480b414c 0
480b4150 0
480b4154 0
480b4158 0
480b415c 0
480b4160 0
480b4164 0
480b4168 0
480b416c 0
480b4170 0
480b4174 0
480b4178 0
480b417c 0
480b4180 0
480b4184 0
480b4188 0
480b418c 0
480b4190 0
480b4194 0
480b4198 0
480b419c 0
480b41a0 0
480b41a4 0
480b41a8 0
480b41ac 0
480b41b0 0
480b41b4 0
480b41b8 0
480b41bc 0
480b41c0 0
480b41c4 0
480b41c8 0
480b41cc 0
480b41d0 0
480b41d4 0
480b41d8 0
480b41dc 0
480b41e0 0
480b41e4 0
480b41e8 0
480b41ec 0
480b41f0 0
480b41f4 0
480b41f8 0
480b41fc 0
480b4200 0
480b4204 0
480b4208 0
480b420c 0
480b4210 0
480b4214 0
480b4218 0
480b421c 0
480b4220 0
480b4224 1f00000
480b4228 0
480b422c 0
480b4230 0
480b4234 0
480b4238 0
480b423c 0
480b4240 20e90080
480b4244 f77
480b4248 0
480b424c 0
480b4250 0
480b4254 0
480b4258 0
480b425c 0
480b4260 401e0
480b4264 40002
480b4268 10002
480b426c 20000
480b4270 0
480b4274 0
480b4278 0
480b427c 0
480b4280 0
480b4284 0
480b4288 0
480b428c 0
480b4290 0
480b4294 0
480b4298 0
480b429c 0
480b42a0 0
480b42a4 0
480b42a8 0
480b42ac 0
480b42b0 0
480b42b4 0
480b42b8 0
480b42bc 0
480b42c0 0
480b42c4 0
480b42c8 0
480b42cc 0
480b42d0 0
480b42d4 0
480b42d8 0
480b42dc 0
480b42e0 0
480b42e4 0
480b42e8 0
480b42ec 0
480b42f0 0
480b42f4 0
480b42f8 0
480b42fc 33020000
mmc reg end:



4a005560 30000
4ae06118 0
4a008920 70000
4ae06190 0
4a0052e4 0
4ae061c8 0
4ae06174 0
4a009848 2
4ae07888 30000
4a005228 208
4a002360 0
4a0051ec 800000
4a009770 101
4a009908 30000
4a005254 0
4ae06154 0
4a009858 2
4a00521c 10a04
4ae061bc 0
4a009750 30000
4a009780 1
4a0097a8 30000
4a008778 30000
4a009328 1040002
4a005234 5
4a005244 1
4a0052b8 204
4a009388 70000
4a005130 2
4a005154 5
4a0098e8 30000
4a008e40 30000
4a005550 30000
4a0093e8 30000
4ae07830 2
4a00516c 81f409
4a009620 30000
4ae06134 0
4a005520 70000
4a005580 30000
4a008210 1
4a008e28 30000
4ae061a0 0
4a009738 2
4a005248 1
4a009800 30000
4a0052d8 5
4a005140 3e
4a0052e8 1
4a0098a8 30000
4a009350 70000
4ae06180 0
4a009798 30000
4ae061c0 0
4a0051e0 5
4a008c00 30000
4ae06108 0
4a0051f0 1
4ae07840 1000002
4ae06170 0
4a0097d8 30000
4a005210 7
4a0098f0 30000
4ae07838 1
4a005220 202
4a009868 30000
4a008158 3
4a00519c 0
4a0086a0 0
4ae061d4 0
4ae06138 0
4ae061c4 0
4a0051f4 1
4ae06114 0
4a008e50 2000001
4a009760 1
4ae061d0 0
4a009878 30000
4a00814c 6004
4a008200 5
4a005160 7
4a0093b0 70000
4a005170 201
4ae061d8 0
4a009120 70000
4a008b30 1
4a0052c0 228
4a0051ac 0
4ae061a8 0
4a00815c 4
4a005568 30000
4a0093d0 8000002
4a009820 30000
4a009220 70000
4a002534 0
4a009020 70000
4a0098d0 30000
4a0093e0 30000
4a009130 70000
4a009850 2
4a005158 4
4a005764 70000
4a009788 30000
4a008160 20a
4ae07878 30000
4a009030 70000
4a005744 30000
4a009890 30000
4a009870 30000
4a0097f0 30000
4ae06194 0
4a009340 70000
4a0097c4 30000
4a009810 1
4a0097b0 30000
4a0051dc 0
4a008780 30000
4a005144 5
4a008164 2
4a008140 7
4a0097c8 30000
4a008150 804
4ae0610c 0
4a0098c8 30000
4ae06130 0
4ae06198 0
4ae06168 0
4ae06184 0
4ae06148 0
4a0051a0 5
4a0051b0 1
4ae0619c 0
4a0056a0 70000
4a009740 30000
4a00821c 0
4a009808 30000
4a009728 30000
4a005290 0
4ae061cc 0
4a005558 30000
4ae0612c 0
4ae06178 0
4a005620 70000
4a009830 30000
4a00818c 4000000
4a00820c 4000000
4a008f28 30000
4a002544 f757fdc0
4a009898 30000
4ae061b0 0
4a009840 2
4a009768 1
4a009904 30000
4a00515c 6
4ae061b8 0
4a0093b8 70000
4a008b38 1
4ae061b4 0
4a009778 1
4a005570 30000
4a0097a0 2
4a0052a4 0
4a005660 70000
4ae06110 2
4a009828 30000
4ae06164 0
4a008b40 0
4ae06160 0
4ae0615c 0
4ae06158 0
4a009028 70000
4a0098e0 30000
4a005284 5
4a005294 1
4a009330 1040002
4a009358 70000
4ae0614c 0
4a005420 70000
4a0093f0 70000
4ae06150 0
4a008180 5
4a0052b4 fa04
4a008190 1
4a00512c 10a04
4a005100 110
4a0097f8 30000
4a008f20 70000
4ae0618c 0
4a0098a0 30000
4a009348 70000
4ae061e0 0
4a0098c0 30000
4a009790 30000
4a009838 1000002
4a0098b8 30000
4a009818 1
4a0097b8 30000
4a008728 1
4a0097d0 30000
4a008e20 1
4a0098f8 30000
4ae07880 30000
4ae0616c 0
4a009860 30000
4ae061ac 0
4a0098b0 30000
4a0052c4 208
4a00513c 204
4ae06120 0
4a009748 30000
4ae06144 0
4a005578 30000
4a005240 0
4a009730 30000
4a0052a8 7
4a005120 7
4a0086b0 0
4ae06188 0
4ae061a4 0
4ae06128 0
cheng, emmc init

cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_complete_init 1
cheng, mmc_startup 1
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_startup 2
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_startup 3
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_startup 4
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_startup 5
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, mmc_send_ext_csd , err=0
cheng, mmc_startup 5.1
cheng, mmc_startup 5.2
cheng, mmc_startup 5.3
cheng, mmc_startup 5.4
cheng, mmc_startup 6
cheng, mmc_startup 7
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, mmc_send_ext_csd , err=0
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, mmc_send_ext_csd , err=0
cheng, mmc_startup 8
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, mmc_send_ext_csd , err=0
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, mmc_send_ext_csd , err=0
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, mmc_send_ext_csd , err=0
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 7
cheng, mmc_send_ext_csd 
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, mmc_send_ext_csd , err=0
cheng, mmc_startup 9
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
mmc_init: 0, time 420 (retries 0)
Foot at common/spl/spl_mmc.c:991/spl_mmc_load_core()
Core = dra7-dsp2-fw.xe66 at 0xaa800000, start = 0x6800, size = 0x1000
cheng, omap_hsmmc_send_cmd 1
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 4
cheng, omap_hsmmc_send_cmd 5
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 6, mmc_stat=0x0
cheng, omap_hsmmc_send_cmd 1
Foot at common/spl/spl_mmc.c:1035/spl_mmc_load_core()
ELF: 0xffffffff 0xffffffff
## No elf image at address 0xaa800000
Error loading remotecore DSP2!,Continuing with boot ...
Foot at common/spl/spl.c:291/spl_load_image()
loaded - jumping to U-Boot...

U-Boot 2016.05-svn23831 (Dec 06 2018 - 15:37:36 +0800)

CPU  : DRA752-GP ES1.1
Model: TI DRA742
Board: DRA74x EVM REV 
DRAM:  1.5 GiB
*** Warning - bad CRC, using default environment

CPU  : DRA752-GP ES1.1
MMC:   no pinctrl for ddr_1_8v
OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

Net:   <ethaddr> not set. Validating first E-fuse MAC
cpsw
Hit any key to stop autoboot:  0 
Wrong Image Format for bootm command
ERROR: can't get kernel image!

[END] 2018/12/6 16:15:46

0 Peter Li79 over 6 years ago in reply to user1897841

TI__Expert 8940 points

Hi, Wen:

the only difference is:
failure : 480b4224 1e00000
normal: 480b4224 1f00000

the discription:
DAT[3:0] line signal level
DAT[3] => bit 23
DAT[2] => bit 22
DAT[1] => bit 21
DAT[0] => bit 20
This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful
in detecting the busy signal level from DAT[0].
The value of these registers after reset depends on the DAT lines level at that time

So, I think our next step should be focused on DAT[0].
1) is it shorted to GND?
2) has it ever been high?
......

0 user1897841 over 6 years ago in reply to Peter Li79

Intellectual 420 points

Hi, Peter:
The resistance between dat[0] and ground is 8.7kΩ.After the serial port is initialized, the print dat[0] is always 0. An oscilloscope measurement found high and low level changes.

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

Hi，Vishal
Do you have any ideas?

0 Vishal Mahaveer over 6 years ago in reply to user1897841

TI__Mastermind 33360 points

Hi Wen Cheng,

Can you confirm again that only delta between these 2 boards is the SOC, everything else is exactly same?
Also, which SDK are you using?

Could you try an experiment by undefining SUPPORTS_ADMA flag?

Regards,
Vishal

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

Hi Vishal,

I am sure that the two boards are the same except for the cpu.SDK is ti-processor-sdk-linux-automotive-dra7xx-evm-03.02.00.03-installer.bin.

I try an experiment by undefining SUPPORTS_ADMA flag, but still did not solve this problem. Log as follow:

omap_hsmmc_send_cmd: timedout waiting on cmd inhibit to clear
mmc_init: -19, time 1038 (retries 0)
spl: mmc init failed with error: -19
MMC: block number 0x1e000 exceeds max(0x0)
kernel, mmc_load_image_raw_os: mmc block read error

0 Peter Li79 over 6 years ago in reply to user1897841

TI__Expert 8940 points

Hi, Wen:

the ID_CODE of the SOC:

DRA750：cpu_id[0x4ae0c204]=0x2b99002f

DRA756：cpu_id[0x4ae0c204]=0x1b99002f

DRA756: SR1.1

DRA750: SR2.0.

the A_DELAY and G_DELAY values listed in the data manual (http://www.ti.com/lit/gpn/dra75 ) should be updated.

0 Vishal Mahaveer over 6 years ago in reply to Peter Li79

TI__Mastermind 33360 points

Hi Wen Cheng,

Could you also share the PADCONF settings of MMC2 pins?
If PULLUP is not enabled, could you try enabling PULLUP for mmc2 pins?

Regards,
Vishal

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

Hi Vishal,

Padconf as follow:

pin[H6]->CMD reg[0x4a0034b0]=0x60001
pin[J7]->CLK reg[0x4a00349c]=0x60001
pin[J4]->DATA0 reg[0x4a0034a0]=0x70001
pin[J6]->DATA1 reg[0x4a0034a4]=0x70001
pin[H4]->DATA2 reg[0x4a0034a8]=0x70001
pin[H5]->DATA3 reg[0x4a0034ac]=0x70001
pin[K7]->DATA4 reg[0x4a00348c]=0x70001
pin[M7]->DATA5 reg[0x4a003490]=0x70001
pin[J5]->DATA6 reg[0x4a003494]=0x70001
pin[K6]->DATA7 reg[0x4a003498]=0x70001

0 Vishal Mahaveer over 6 years ago in reply to user1897841

TI__Mastermind 33360 points

Pull ups are enabled..

How many boards show the MMC init failure?

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

A total of four DRA750 boards were posted, three emmc init failed, and one posted a problem.

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

Hi Vishal,

DRA756 PADCONF as follow:

pin[H6]->CMD reg[0x4a0034b0]=0x60001
pin[J7]->CLK reg[0x4a00349c]=0x60001
pin[J4]->DATA0 reg[0x4a0034a0]=0x60001
pin[J6]->DATA1 reg[0x4a0034a4]=0x60001
pin[H4]->DATA2 reg[0x4a0034a8]=0x60001
pin[H5]->DATA3 reg[0x4a0034ac]=0x60001
pin[K7]->DATA4 reg[0x4a00348c]=0x60001
pin[M7]->DATA5 reg[0x4a003490]=0x60001
pin[J5]->DATA6 reg[0x4a003494]=0x60001
pin[K6]->DATA7 reg[0x4a003498]=0x60001

DRA750 PADCONF as follow:

I am trying to configure the DRA750's pin conf to be DRA756. The result failed. I can't write 0x60001 to the data pin. I found that bit16 can't write in. I can work emmc after adding a pull-up resistor outside the data pin.Why can't bit16 write? DRA756 data pin bit16 can be written.

Thank you.

0 Vishal Mahaveer over 6 years ago in reply to user1897841

TI__Mastermind 33360 points

What is the SYSBOOT[15] setting on the board?

0 user1897841 over 6 years ago in reply to Vishal Mahaveer

Intellectual 420 points

Hi Vishal,

SYSBOOT[15] is high level (3.3V).

0 Vishal Mahaveer over 6 years ago in reply to user1897841

TI__Mastermind 33360 points

Hi,

Comment from our H/W team:

SYSBOOT[15] = 1 will disable the internal pulls on the DAT lines. This means the data bus will be floating and may be mistakenly read as a '0' (busy state) by the slave eMMC device. In this case, the external PU resistors (as specified by JEDEC spec) have to be present; this is to ensure DAT line will not be floating/misread as busy, and the eMMC device will be able to drive back data

Regards,
Vishal

Processors

Processors forum

Linux: DRA750 MLO halt mmc_init