RTOS: In captured video frame through VIP/VPDMA,every alternate lines in frame look missing

Hi Jeyaseelan,

Could you please check if there is really alternate lines missing? It seems fields are swapped.
Btw, how are merging two fields for interlaced input? VIP outputs individual fields. are you providing two buffer pointers to the display driver?
Essentially how do capture two fields and display them on display driver?

Rgds,
Brijesh

Hi Brijesh,

Actually as per the driver code , the vpdma list complete interrupt is triggered for VIP1 interrupt line 70 over cross bar 392 ) . i guess this interrupt is triggered on reception of every field. In the ISR, Field_ID component is read from the register "VIP_OUTPUT_PORT_A_SRC_FID 0x48975A20" for source 0 at bit 0 . If it is read as odd field ,then DDR start buffer is adjusted to buff+ 720 for Y and UV and vpdma list is again reconfigured for next field capture for this new address. Have attached the code snippet below.

static void VPDMAListCompleteIsr(uint32_t argument) // ISR for VPDMA List complete
{
BevCameraPort_t port = (BevCameraPort_t)argument;

uint8_t *bufs[] = {(uint8_t *)VID1_MEM_ADDR, (uint8_t *)VID1_MEM_ADDR_UV, NULL};
vp_get_frame(port, (void **)bufs);
}

void vp_get_frame(enum vip_port port, void *bufs[]) // Get next Field
{
uint32_t vpdma_base = vp_to_vpdma_base(port);

start_vpdma(vpdma_base, (uint8_t **) bufs);
}

static void start_vpdma(uint32_t vpdma_base, uint8_t *bufs[])
{
dma_addr_t *dma_addrs = NULL;
int drop_data = 0u;

if (bufs)
{
dma_addrs = (dma_addr_t *)bufs;
drop_data = 0;
if (vpdma_list_busy(vpdma_base, VPDMA_LIST_NUM))
{
Tr_Warn("vip1 vpdma list0 busy, cannot post");
return; // nothing to do
}
if (vp_is_odd_frame())
{
*dma_addrs += VIP_MAX_WIDTH;
*(dma_addrs + 1) += VIP_MAX_WIDTH;
}
vpdma_update_dma_addrs(&g_vpdma_list, dma_addrs, drop_data); // Updating address for next field capture
vpdma_submit_descs(vpdma_base, &g_vpdma_list, VPDMA_LIST_NUM);
}
else
{
dma_addrs = (dma_addr_t *)NULL;
drop_data = 1;
}
}

Can you let me know if this above logic needs any change ?

With regards,
Jeyaseelan

bool vp_is_odd_frame()
{
return (bool)(readl(VIP_OUTPUT_PORT_A_SRC_FID) & 0x2);
}

#define VIP_MAX_WIDTH 720
#define VID1_MEM_ADDR 0x9A000000
#define VID1_MEM_ADDR_UV 0x9A0E1000

VID1_MEM_ADDR & VID1_MEM_ADDR_UV are destination address for the video frame in co-planar yuv (4:2:0) format.

With regards,
Jeyaseelan

Hi Brijesh,

Thanks for the support . I have re-arranged these lines adjusting target start of memory by checking the Bit-1(current field) of register "VIP_OUTPUT_PORT_A_SRC_FID 0x48975A20" .Before it was tested for Bit-0(previous field).This resulted in swap of lines. Now the lines are are properly and the picture looks clear.

bool vp_is_odd_frame()
{
// return (bool)(readl(VIP_OUTPUT_PORT_A_SRC_FID) & 0x1);
return (bool)(readl(VIP_OUTPUT_PORT_A_SRC_FID) & 0x2);
}

With regards,
Jeyaseelan

Hi Brijesh,

If you have time ,can you just look in what could be the cause of issue in this thread?

RTOS: Offset of few horizontal lines are observed before the start of frame.

With regards,
Jeyaseelan

Hi Jeyaseelan,

I am sorry, i could not get the question. I thought you said that the issue is resolved after you swapped buffer pointers for both even and odd fields. isn't it correct?

Rgds,
Brijesh

Please share link to the thread.. let me see if i can help.