RTOS/AM5728: Can't initial clock and module (BOARD_INIT_MODULE_CLOCK) when debuging SBL_custom_am572x_board

Shreek

Part Number: AM5728
Other Parts Discussed in Thread: TPS659037

Tool/software: TI-RTOS

I created my own custom board library and built my own custom SBL_ccs_project. But the function Board_init(boardCfg) never return unless i commented the line 88 "BOARD_INIT_MODULE_CLOCK |" just like this

//line 87 to 98 in sbl_main.c

    boardCfg |= BOARD_INIT_UNLOCK_MMR |
//        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_DDR |
        BOARD_INIT_UART_STDIO |
        BOARD_INIT_WATCHDOG_DISABLE;

    /* Configure AVS voltage for the selected OPP to the voltage rails. */
    SBL_Configure_AVS(oppMode);

    /* Board Library Init. */
    Board_init(boardCfg);

By the way. my_custom_am5728_board_clock.c is the copy of evmAM572x_clock.c without any changing. And my custom board hardware has been tested normal. Why I can't initial my board(Board_init()) with boardCfg containing 'BOARD_INIT_MODULE_CLOCK'?

over 6 years ago

0 lding over 6 years ago

TI__Guru* 95265 points

Hi,

As you have a CCS project, I think it would be easier to debug. The flag BOARD_INIT_MODULE_CLOCK is passed into board library, calling Board_moduleClockInit(), which you copied from evmAM572x_clock.c. This function initializes multiple PRCM domains, you can step through the code to see which one is stuck?

Regards, Eric

0 Shreek over 6 years ago in reply to lding

Intellectual 990 points

Thank you for replying.
I linked custom_board_clock.c(copy of evmAM572x_clock.c) to my own sbl_ccs_project and rebuild it and it works,but it failed to boot app, message shows bellow:
teraterm

**** PDK SBL ****
SBL Revision: 01.00.09.01 (Dec 9 2018 - 12:37:32)
Begin parsing user application

SD Boot - file open completed successfully
Invalid magic number in Single image header
Jumping to user application...

what does 'Invalid magic number in Single image header' means? I have only one single core app which converted by out2rprc.exe.

0 lding over 6 years ago in reply to Shreek

TI__Guru* 95265 points

Hi,

Then you don't have the PRCM clock enabling stuck issue, but the boot a SD application failed. See:

Step 1: Conversion to RPRC format conversion

Firstly, application executable is converted from ELF/COFF format (.out) to custom TI Rprc binary image using out2rprc tool. This tool strips out the initialized sections from the executable file (i.e. *.out) and places them in a compact format that the SBL can understand. The output (bin) file is typically much smaller than the original executable (out) file.

The rprc files are intermediate files in a format that is consumed by MulticoreImageGen tool that generates the final binary.

See: pdk_am57xx_1_0_12\packages\pdkAppImageCreate=====>\pdk_am57xx_1_0_12\packages\ti\boot\sbl\tools\scripts\AM57xImageGen for the process.

Regards, Eric

0 Shreek over 6 years ago in reply to lding

Intellectual 990 points

Thank you for replying.

Finally I got app image successfully. Then I use sbl_ccs_project to load the sbl.out to my custom board and the app on SD can be loaded normally and running normally. but when I converted the sbl.out to MLO then loaded app on SD and it can't work and nothing comes out from debug uart (115200,N,8,1). I got my MLO as bellow:

step1: convert sbl.out to sbl.bin using arm-none-eabi-objcopy.exe

arm-none-eabi-objcopy.exe --gap-fill=0xff -O binary SBL.out SBL.bin

step2: convertsbl.bin to sbl.tiimage using tiimage.exe:

tiimage.exe 0x40331000 NONE sbl.bin sbl.tiimage

step3: rename sbl.tiimage to MLO, copy MLO to SD card(app is already inside)

step4: power on custom board:

by the way, sysboot[5:0]=[100010]. and the PMIC_POWERHOLD(Pin G9 of TPS659037) is always pulled HIGH,

Is there nay mistake?

I also recreated sbl.out of GP EVMAM572x using step1-step4 above, the recreated MLO works normally on GP EVM AM572x. But WHY it can't work on my custom board?

0 lding over 6 years ago in reply to Shreek

TI__Guru* 95265 points

Hi,

Good to know you have SBL,out loaded via CCS and open APP on SD card worked. Then the issue is how the SBL.out converted to MLO. I looked at the pdk_am57xx_1_0_12\packages\ti\boot\sbl\board\evmAM572x\build\makefile

$(SBLBINDIR)/$(EXE): $(SRC_OBJS) $(SRC_DRV_OBJS) $(ENTRY_OBJ) $(SBLBINDIR)/.created $(SBLOBJDIR)/.created
@echo linking $(SRC_OBJS) $(SRC_DRV_OBJS) $(ENTRY_OBJ) into $@ ...
@$(CC) $(SRC_OBJS) $(SRC_DRV_OBJS) $(ENTRY_OBJ) $(INTERNALLINKDEFS) -Wl,-Map=$(SBLBINDIR)/sbl.map -o $@
$(BIN) $(BINFLAGS) $(SBLBINDIR)/sbl.out \
$(SBLBINDIR)/sbl.bin
$(SBL_SRC_DIR)/tools/tiImageGen/bin/$(TIIMAGE_EXE) $(IMG_LOAD_ADDR) $(BOOTMODE) \
$(SBLBINDIR)/sbl.bin $(SBLBINDIR)/MLO;

This is the way you should do conversion.

Where:

BIN = $(TOOLCHAIN_PATH_A15)/bin/$(CROSS_TOOL_PRFX)objcopy

BINFLAGS = -O binary

TIIMAGE_EXE = tiimage.exe

BOOTMODE mmcsd

IMG_LOAD_ADDR = 0x40331000

You can build the MLO for evmAM572x and look at the build log how that was converted.

Regards, Eric

0 Shreek over 6 years ago in reply to lding

Intellectual 990 points

The MLO still can't work which converted by the way you offered.

Maybe there is something wrong with Board_DDR3Init function, as the ddr is initialed normal by gel via ccs.

Only EMIF1 is used on my custom board based evmAM572x, I used emif tools to generate a function,which is used to replace 'AM572x_set_emif1_params_ddr3_532(SOC_EMIF1_CONF_REGS_BASE);' in AM572x_ddr_config.gel, also 'AM572x_set_lisa_maps()' is modified,all the changes to AM572x_ddr_config.gel list as below:

//AM572x_set_emif1_params_ddr3_532 is replace by the function
static void AM572x_DDR3L_532MHz_custom_board_emif1 (uint32_t base_addr)            
{           
    SDRAM_TIM_1 = 0xCEEF36B3U;          
    SDRAM_TIM_2 = 0x30BF7FDAU;          
    SDRAM_TIM_3 = 0x407F88A8U;          
            
    SDRAM_REF_CTRL = 0x00001035U;           
    SDRAM_REF_CTRL_INIT = 0x000040F1U;          
    SDRAM_CONFIG = 0x61851B32U;         
            
    EMIF_PHY_READ_LATENCY = 0xBU;           
    EMIF_PHY_INVERT_CLKOUT = 0x1U;          
    EMIF_PHY_HALF_DELAY_MODE = 0x1U;            
    EMIF_PHY_DQ_OFFSET = 0x40U;         
    EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U;          
            
    DISABLE_READ_LEVELING = 0x0U;           
    DISABLE_READ_GATE_LEVELING = 0x0U;          
    DISABLE_WRITE_LEVELING = 0x0U;          
            
    /* EXT_PHY_CTRL_xx are used only in case of  HW_LEVELING_ENABLED  =  0*/            
    /* EMIF_PHY_FIFO_WE_SLAVE_RATIO (RD_DQS_GATE) */            
    EXT_PHY_CTRL_2 = 0x006B0093U;           
    EXT_PHY_CTRL_3 = 0x006B0093U;           
    EXT_PHY_CTRL_4 = 0x006B0097U;           
    EXT_PHY_CTRL_5 = 0x006B0092U;           
    EXT_PHY_CTRL_6 = 0x006B006BU;           
            
    /* EMIF_PHY_RD_DQS_SLAVE_RATIO */           
    EXT_PHY_CTRL_7 = 0x00320032U;           
    EXT_PHY_CTRL_8 = 0x00320032U;           
    EXT_PHY_CTRL_9 = 0x00320032U;           
    EXT_PHY_CTRL_10 = 0x00320032U;          
    EXT_PHY_CTRL_11 = 0x00320032U;          
            
    /* EMIF_PHY_WR_DQS_SLAVE_RATIO */           
    EXT_PHY_CTRL_17 = 0x00400058U;          
    EXT_PHY_CTRL_18 = 0x00400058U;          
    EXT_PHY_CTRL_19 = 0x00400054U;          
    EXT_PHY_CTRL_20 = 0x00400059U;          
    EXT_PHY_CTRL_21 = 0x00400040U;          
}          


static void AM572x_set_lisa_maps()
{
	int memmap_intl_flag=0;
	
    /* Reset all LISA MAPs */
    HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0U);
    HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0U);
    HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_2, 0U);
    HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_3, 0U);
    HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0U);
    HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0U);
    HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_2, 0U);
    HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_3, 0U);    
		
    printf("       Two EMIFs in non interleaved mode (1GB total)\n");
    /* MA_LISA_MAP_i */
    WR_MEM_32(0x482AF040, 0x80600100);
    WR_MEM_32(0x482AF044, 0xC0600200);
    /* DMM_LISA_MAP_i */
    WR_MEM_32(0x4E000040, 0x80600100);
    WR_MEM_32(0x4E000044, 0xC0600200);    		
}

The AM572x_ddr_config.gel is loaded and worked normally,but i don't know how to add this changes to board/src/custom_board_ddr.c,which is copied from board/src/evmAM572x_ddr.c. I modify my board/src/custom_board_ddr.c as bellow:

/* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
Board_STATUS Board_DDR3Init()
{
    int retVal = BOARD_SOK;
    CSL_emifObj     emifObj1;
    CSL_emifHandle  hEmif1 = &emifObj1;
    CSL_emifDdrConfig ddr3Config1;

    CSL_ckgen_cm_core_aonRegs *hCkgenCmCoreAon  =     (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
    CSL_control_core_padRegs  *hCtrlCorePad     =     (CSL_control_core_padRegs *)  CSL_MPU_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_REGS;
    CSL_control_core_wkupRegs *hCtrlCoreWkup    =     (CSL_control_core_wkupRegs *) CSL_MPU_CTRL_MODULE_WKUP_CORE_REGISTERS_REGS;
    CSL_DmmRegs      *hDmmCfg   = (CSL_DmmRegs *) CSL_MPU_DMM_CONF_REGS_REGS;
    CSL_MampuLsmRegs *hMampuLsm = (CSL_MampuLsmRegs *) CSL_MPU_MA_MPU_LSM_REGS;

    hEmif1->regs = (CSL_emifRegsOvly)CSL_MPU_EMIF1_CONF_REGS_REGS;

    /* DLL override disable =0 ; enable = 1 */
    hCkgenCmCoreAon->CM_DLL_CTRL_REG = 0x00000000;

    /*
     * CONTROL_DDR3CH1_0 -- channel_1 CMDs
     * -- 40Ohm Ron (011)
     * -- SR=slowest-3 (111) on CMDs
     * -- CLK SR=slow (011)
     * -- No pulls (00)
     */
    hCtrlCorePad->CONTROL_DDRCACH1_0 = 0x80808080;

    /*
     * CONTROL_DDRCH1_0 -- channel_1 DATA byte 0+1
     * -- 40Ohm Ron (011)
     * -- SR=faster (001)
     * -- Pull-up (10) on DQS
     * -- No pull (00) on DQ
     */
    hCtrlCorePad->CONTROL_DDRCH1_0 = 0x40404040;

    /*
     * CONTROL_DDRCH1_1 -- channel_1 DATA byte 2+3
     * -- 40Ohm Ron (011)
     * -- SR=faster (001)
     * -- Pull-up (10) on DQS
     * -- No pull (00) on DQ
     */
    hCtrlCorePad->CONTROL_DDRCH1_1 = 0x40404040;

    /*
     * CONTROL_LPDDR2CH1_0
     * -- channel_1 LPDDR2 CMD PHYs IOs not used
     */
    hCtrlCorePad->CONTROL_DDRCH1_2 = 0x00404000U;

    /*
     * CONTROL_DDR3CH2_0 -- channel_2 CMDs
     * -- 40Ohm Ron (011)
     * -- SR=slowest-3 (111) on CMDs
     * -- CLK SR=slow (011)
     * -- No pulls (00)
     */
    hCtrlCorePad->CONTROL_DDRCACH2_0 = 0x80808080;

    /*
     * CONTROL_DDRCH2_0 -- channel_2 DATA byte 0+1
     * -- 40Ohm Ron (011)
     * -- SR=faster (001)
     * -- Pull-up (10) on DQS
     * -- No pull (00) on DQ
     */
    hCtrlCorePad->CONTROL_DDRCH2_0 = 0x40404040;

    /*
     * CONTROL_DDRCH2_1 -- channel_2 DATA byte 2+3
     * -- 40Ohm Ron (011)
     * -- SR=faster (001)
     * -- Pull-up (10) on DQS
     * -- No pull (00) on DQ
     */
    hCtrlCorePad->CONTROL_DDRCH2_1 = 0x40404040;

    /*
     * DDRIO_0 -- VREF cells
     * (CH1 DQ3/0 INT 2uA / Cap to GND / CMD1/0 DDR3 INT-OUT 32uA / Cap to GND)
     */
    hCtrlCorePad->CONTROL_DDRIO_0 = 0x00094A40U;

    /*
     * DDRIO_1 -- VREF cells
     * (CH1 OUT 32uA Cap to GND / CH2 DQ3/0 INT 2uA / Cap to GND / CH2 OUT 32uA Cap to GND)
     */
    hCtrlCorePad->CONTROL_DDRIO_1 = 0x04A52000U;

    /*
     * EMIF1_SDRAM_CONFIG_EXT
     * -- cslice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)
     */
    /* EMIF1_EN_ECC = 0 */
    hCtrlCoreWkup->EMIF1_SDRAM_CONFIG_EXT = 0x0001C127U;


    ddr3Config1.emifDdrParam.ddrPhyCtrl = hEmif1->regs->DDR_PHY_CONTROL_2;

    ddr3Config1.emifDdrParam.sdramTim1 = 0xCEEF36B3U;//SDRAM_TIM_1 = 0xCEEF36B3U;
    ddr3Config1.emifDdrParam.sdramTim2 = 0x30BF7FDAU;//SDRAM_TIM_2 = 0x30BF7FDAU;
    ddr3Config1.emifDdrParam.sdramTim3 = 0x407F88A8U;//SDRAM_TIM_3 = 0x407F88A8U;

    ddr3Config1.emifDdrParam.sdramCfg = 0x61851B32U;//SDRAM_CONFIG =          0x61851B32U;
    ddr3Config1.emifDdrParam.sdramCfg2 = 0x08000000U;
    ddr3Config1.emifDdrParam.sdramRefCtrl = 0x00001035U;//SDRAM_REF_CTRL =        0x00001035U;
    ddr3Config1.emifDdrParam.zqConfig = 0x5007190BU;
    ddr3Config1.emifDdrParam.sdramPwrMngtCtrl = 0x00000000U;

    ioDftLogicCtrl = hEmif1->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL;
    readWriteLvlRampWin = hEmif1->regs->READ_WRITE_LEVELING_RAMP_WINDOW;

    ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio      = 0x80U;//    EMIF_PHY_CTRL_SLAVE_RATIO   = 0x80U;
    ddr3Config1.emifDdrPhyParam.dqOffset            = 0x40U;//    EMIF_PHY_DQ_OFFSET          = 0x40U;
    ddr3Config1.emifDdrPhyParam.gateLevelInitMode   = 0x0U;//
    ddr3Config1.emifDdrPhyParam.fifoWeInDelay       = 0x0U;
    ddr3Config1.emifDdrPhyParam.ctrlSlaveDelay      = 0x0U;
    ddr3Config1.emifDdrPhyParam.readDqsSlaveDelay   = 0x0020U;
    ddr3Config1.emifDdrPhyParam.writeDqsSlaveDelay  = 0x0060U;
    ddr3Config1.emifDdrPhyParam.writeDataSlaveDelay = 0x80U;


    ddr3Config1.emifDdrPhyParam.gateLevelRatio      = 0x00U;
    ddr3Config1.emifDdrPhyParam.writeDqsSlaveRatio  = 0x60U;
    ddr3Config1.emifDdrPhyParam.fifoWeSlaveRatio    = 0xBBU;
    ddr3Config1.emifDdrPhyParam.useRank0Delays      = 1U;

    ddr3Config1.emifDdrPhyParam.gateLevelNumDq0     = 0xFU;
    ddr3Config1.emifDdrPhyParam.writeLevelNumDq0    = hEmif1->regs->EXT_PHY_CONTROL_36;

    retVal = emifConfigureDdr3(hEmif1, &ddr3Config1, 1U);


    if(BOARD_SOK == retVal)
    {
        /* Reset all LISA MAPs */
        hMampuLsm->MAP_0 = 0U;
        hMampuLsm->MAP_1 = 0U;
        hMampuLsm->MAP_2 = 0U;
        hMampuLsm->MAP_3 = 0U;
        hDmmCfg->LISA_MAP[0U] = 0U;
        hDmmCfg->LISA_MAP[1U] = 0U;
        hDmmCfg->LISA_MAP[2U] = 0U;
        hDmmCfg->LISA_MAP[3U] = 0U;

        //single 1GB DDR,not in interlaced mode
        /* MA_LISA_MAP_i */
        hMampuLsm->MAP_0 = 0x80600100;
        hMampuLsm->MAP_1 = 0xC0600200;
        /* DMM_LISA_MAP_i */
        hDmmCfg->LISA_MAP[0U] = 0x80600100;
        hDmmCfg->LISA_MAP[1U] = 0xC0600200;
    }
    else
    {
        retVal = BOARD_INIT_DDR_FAIL;
    }
    return retVal;
}

Q1. How to modify custom_board_ddr.c based on emif tools?

0 lding over 6 years ago in reply to Shreek

TI__Guru* 95265 points

Shreek,

Sorry I missed this thread. Do you still have the issue or already resolved? Your final question here is: you used the EMIF tool to generate the DDR3 configuration, but how do you convert that into C code for board library, is that correct?

Regards, Eric

0 Shreek over 6 years ago in reply to lding

Intellectual 990 points

Yes. Maybe there is something wrong with my Board_DDR3Init() ,which is modified based on the result of EMIF tools. So what is the standard way to modify Board_DDR3Init using EMIF tools?

0 lding over 6 years ago in reply to Shreek

TI__Guru* 95265 points

Hi,

I checked the EMIF tool expert, unfortunately the customer has to manually take the results of the EMIF tool and plug them into the appropriate registers in the board configuration function. The current EMIF tool for AM57x needs a lot of changes to align with current software offerings, especially for RTOS. So there is no quick way for this. Sorry!

Regards, Eric

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RTOS/AM5728: Can't initial clock and module (BOARD_INIT_MODULE_CLOCK) when debuging SBL_custom_am572x_board