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RTOS/TDA3: Video input spec

Sung-IL
Mastermind 29890 points

Part Number: TDA3

Tool/software: TI-RTOS

Dear Champ,

Could you please check if below camera sensor digital output can be received into VIP ports of TDA3?

MC is Master Clock.

1. I think there should be no issue if MC will be connected to Pixel Clock of VIP ports with 8bit mode and ignore PSYNC, but want to check with you again because my customer want to confirm again if additional FPGA will be needed or not between camera senor module and TDA3 VIPs.

2. I also want to check with you if there is no issue when there was a gap(tag) between VSYNC and HSYNC as you see in above.

3. if there is some information in the 'tag'(green region) in above, there is no way to check the value of 'tag', right?

4. I think there is no issue to get ancillary data(blue region) in the HSYNC deactive region, right?

5. This is mono sensor. Is it possible to receive Y data only?

Thanks and Best Regards,

SI.

  • 0
    TI__Expert 4935 points
    1. Yes. You need to connect the MC, VSYNC and HSYNC to VIP. I am not sure what is special about Pixel Sync. VIP expects the clock to toggle for every data. SO looks like MC matches that rather than PSYNC
    2. This should not be an issue
    3. In HSYNC/VSYNC mode of VIP parser, the VIP can capture the entire frame including the VBLK and HBLK data. So you can use this to get the required data in the blanking period
    4. Same as above
    5. I assume the input is Y and CbCr interleaved (MSB and LSB). In this case you can use the YUV422SP output to get the MSB in one buffer and LSB in another buffer.