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Questions on 6437 clock rate

Anonymous
Anonymous

Other Parts Discussed in Thread: TMS320DM6437

Hi,

I would like to ask some questions on chip clock rates:


In the page of DM6437, I have found four columns in the parametric section: TMS320DM6437-400, TMS320DM6437-500, TMS320DM6437-600, TMS320DM6437-700.

And in Features section above, the listed four Instruction Cycle Time corresponds to 1 second divides 400M, 500M, 600M, 700M:

clock cycle said:

1 second=1000M ns

1000/400=2.5 ns
1000/500=2 ns
1000/600=1.67 ns
1000/700=1.43 ns



Are these just the same chip with different external crystal clock supplied, like hobbist's overclocking of Intel/AMD processors?

However, in configuring the RTSC platform I found that the default clock speed for DM6437 is 594MHz. Since the external crystal clock rate on my EVM (from a third-party provider rather than TI or Spectrum) is 27MHz, we can infer from these two numbers that because:
594=27×22

Then the internal PLL does a multiplication by 22.


                           

Then 600MHz is not the accurate clock cycle rate but only a nominal value. But usually the external reference crystal oscillator is 27MHz, so we only have close multiples of 27MHz which made all 400, 500, 600, 700MHz nominal values:

27×15=405 ~ 400
27×18=486 or 27×19=513 ~ 500
27×22=594 ~ 600
27×26=702 ~ 700

Is this correct? If yes, for nominal 500Mhz, is it actually 486 or 513MHz?

 


                 

I also found on page 9, SPRS345d, TMS320DM6437 Digital Media Processor, that PLL can multiply between x14 to x30. How can this be configured by software? Do they actually correspond to different chips, just as DM6437 has 361 and 376 pin BGA packages? Are the PLL multiplication hardwired?

 

        

Sincerely,
Zheng

  • We guarantee proper operation up to the device's rated maximum speed.  You have the flexibility to choose the speed of the external input clock and you have the flexibility to program the PLL.  However, you are required to make sure the resulting clock speed stays within our specs.

    The PLL multiplication is not hard-wired.  It's programmable.  See Chapter 5 "PLL Controller" of the DM643x DSP Subsystem Guide for more details.

  • Anonymous
    0 Anonymous in reply to Brad Griffis

    Dear Brad,

    Is there any way to know this maximum clock rate information?

    1. I used a magnifier to look at the top of the DM6437 chip on my EVM board but could find any information indicating maximum clock rate.

    DAVINCI

    TMS320

    DM6437ZWT

    $NC-xxxxxxx

     

    2. At memory location 0x01c40910, which for DM6437 is  PLL's Multiplier Control Register (PLL1_PLLM), the value is 0x00000015, which means the multiplier value is  21+1=22. The external reference oscillator is 27MHz and therefore the chips seems to work at 594 MHz. But how can I find out its maximum clock rate? The manual (from a third-party provider) of the EVM was quite obscure on this.

     

     

    Sincerely,

    Zheng

  • Zheng Zhao said:
    Is there any way to know this maximum clock rate information?

    It's not on the package, just the part number you ordered. 

     

    Zheng Zhao said:
    The external reference oscillator is 27MHz and therefore the chips seems to work at 594 MHz. But how can I find out its maximum clock rate? The manual (from a third-party provider) of the EVM was quite obscure on this.

    In this case the DM6437 EVM technical reference guide states on page 12 for "key features":

    "A Texas Instruments DM6437 processor operating up to 600 Mhz."

     

  • Anonymous
    0 Anonymous in reply to Brad Griffis

    Dear Brad,

    I am not using a Spectrum EVM.

    Including the tariff, it takes $price × 10 (RMB) to buy a Spectrum EVM in China, so I simply got a cheaper one.

    The EVM has its own manual  and it seems to state that the maximum clock rate is 700MHz, so they should have used the fatest chip of 6437.

    But after checking with the PLL1_PLLM register in run time I found it to be 21+1=22, so the chip is actually running at 27 × 22 =594MHz.

    Mostly likely there is nothing strange at all here. They bought the fatest (expensive) chip, and simply initialized the PLL to let the chip run at some 100MHz lower than its maximum clock rate to achieve a wider "safety margin". Is this possible?

     

    I still have two additional questions:

    1. What does the nominal 700MHz actually refer to? 700±5%?

    2. Although the manual states maximum 700MHz  rate, I still want to ascertain it myself. Is there any way to read that from the chip? For maximum 400MHz, 500MHz, 600MHz and 700MHz chip, do they differ in the internal silicon/circuit structure? If they the silicon are precisely identical, where comes this difference? From material? But they are all made of silicon, so where can the material difference come from?

     

     

     

    Sincerely,

    Zheng

     

  • Anonymous
    0 Anonymous in reply to Brad Griffis

    Dear Brad,

    Brad Griffis said:

    The PLL multiplication is not hard-wired. It's programmable. See Chapter 5 "PLL Controller" of the DM643x DSP Subsystem Guide for more details.

     

    If my reference oscillator is 27MHz and I set PLL1_PLLM to X28, which results in 27 ×(28+1)= 783 MHz, what will happen?

    1. The chip get burned?
    2. The chip somehow "sleep" or "refuse to work" as a measure of self-protection?

     

     

    Zheng

     

     

  • Zheng Zhao said:

    If my reference oscillator is 27MHz and I set PLL1_PLLM to X28, which results in 27 ×(28+1)= 783 MHz, what will happen?

    1. The chip get burned?
    2. The chip somehow "sleep" or "refuse to work" as a measure of self-protection?

     

    Operation outside our specifications is undefined.  For example, it might work fine on some devices but not others.  It might work ok at some temperatures but not others.  Often times you'll see "over clockers" increasing the core voltage as well (also a "no no" from TI perspective).  This would shorten the lifetime of the device.

  • Anonymous
    0 Anonymous in reply to Brad Griffis

    Dear Brad,

    Got it, thanks.

     

    Zheng

  • Hi Zeng,

     

    I want to raise mydm6437 clock rate like you. could you do this succesfully? And how did you change clock rate? i saw that PLL1_PLLM variable in "evmdm6437.h" i try to change this variable. but i coulndt see any change. did i do right change?

     

    Thanks!

  • Ayhan,

    You could modify address 0x01c40910 to values other than its default value and it would work.

     

     

    After having determined the PLL value that suits your need, you might modify the GEL file or set 0x01c40910 value in initialization routines.

     

    Zheng

  • Thanks Zheng,

     

    now i can change PPL value. i want used this clock change for real time video proceesing. when i change PLL1_PLLM = 0x00000026 my fps is improve but i coulndnt see this improvement in video. but when i cnahge PLL1_PLLM 0x00000010 fps and video improve. where is the problem in here? Logically, my fps and video must be good at 16. 

  • is anyone have an idea this is very urgent station for me?

  • If you change PLL1 Multiplier to 26, then you actually get 27MHz (I assume you use 27MHz input) × (26+1) = 729 MHz clock rate, and for this to work you probably should use -7 devices (means you DM6437 chip's maximum clock should be marked as 700 MHz, see sprs345d p.159) and you also need to use 1.2V DSP core power supply rather than 1.05V.

     

    When you say "video would improve", do you mean back end output from VPBE? Which output format (VGA, LCD, etc.) do you use? Could you provide more detailed information of the problem you met?

     

     

    Zheng

     

     

  • My video output format is PAL(tv). i can tell you my problem like this. when i set PLL1_PLLM at beginning of the may main program file like this PLL1_PLLM = 0x00000026. i saw that my fps is 30 but my video look like 10 or 15 fps. but when i set PLL1_PLLM = 0x00000010 then measure fps i saw that my fps is 25 and video how is must be at 25 fps.

  • Ayhan,

    I suggest you ask the question in another thread so that TI employees would more likely to look at it. This thread was originally about PLL multiplier, and since you have already succeeded in modifying the value, your new question on video processing should be discussed in a separate thread.

     

    Zheng