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Removing termination resistors for DDR2 with DM6467 and AM3505

Rizwan Hirani
Intellectual 450 points
Other Parts Discussed in Thread: AM3505

We are considering TMS320DM6467ZUT7 and AM3505AZCNA on one of the our product which is in early design phase.

As per the data sheets of both parts DDR2 SDRAM interface requires termination. 

But because of space constraint on PCB we cannot provide terminations as per recommendations.

Can anybody please suggest what additional care we should take care in schematic and layout for DDR2 interface?As we are targeting  FCC part-B certification for this product. Please share with us, If you have any reference designs/Layout which is FCC part-B certified without terminations on DDR2.

Thanks,
Rizwan Hirani

  • 0
    TI__Expert 8260 points

    DDR2 expert is on vacation till 30th Nov. I will get back to you as soon as I hear from him.

    Regards, Srirami.

  • 0
    TI__Intellectual 1610 points

    For DM6467, the terminations are optional for the DDR2 interface, see section 7.10.2.9 of the data sheet.

    For AM3505, terminations are not optional due to the higher strength buffers used on its DDR interface versus the DM6467.

    The termination requirements were driven to meet overshoot and undershoot signaling requirements rather than FCC requirements.  Meeting FCC requirements goes beyond just the DDR interface and requires careful PCB design.  Generally, all of the following will help with reducing EMI radiation:

    1. Add serial terminators to slow down edges and calm ringing.
    2. Ensure that each high speed signal trace has an uninterrupted return path to ground, preferably on a ground plane.  For DM6467 this is required on the DDR2 interface.  It may also be required on AM3505.
    3. Use as many bypass capacitors as you can fit and connect them with the best possible connections, meaning if you share vias only share them with one cap on the top of the board and one on the bottom of the board.  Connect them with the widest traces possible to their connecting vias.  Use the largest via you can fit for them.  Do the same with power and ground pins on your devices.  It is more important to use many physically small caps to bring down the parasitic inductance of the power system rather than trying to build up capacitance.  You should use the smallest physical sized cap you can reliably obtain at the highest capacitance available.  Physically smaller caps will also radiate less.
    4. Add layers to the PCB and route high speed signals inside shielded by ground planes.
    5. Place the PCB in a metal enclosure (Faraday cage).

    All of this said, I have had several customers use the DDR2 layout rules with or without serial termination for the DM6467 and earlier devices going back to 2005.  Either choice has been reliable without complaint of FCC certification issues.  The AM3505 represents a newer DDR2 controller design with more powerful buffers, and this limits it to boards with serial termination.  Note that serial termination is only required on Am3505 for the clock, address, and control lines.  The data lines use the built in ODT capability.

    My suggestion is to get a handle on your form factor requirements and make an attempt at PCB placement.  Contact your TI FAE and we can review this placement and most likely work out one that is compliant with your requirements and our PCB specification.

    -Mike