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RTOS/AMIC120: Are PRU-ICSS1 and A9 synchronized in TIDEP0025 project?

U-SK
Genius 5840 points
Part Number: AMIC120
Other Parts Discussed in Thread: TIDEP0025

Tool/software: TI-RTOS

Hello,

I have two questions.

1.In the project of TIDEP0025, do PRU-ICSS 1 and A 9 operate in synchronism using timers etc?

2.When acquiring EtherCAT data every 250μs(4kHz) without missing, and executing TIDEP0025 motor control, how much should it be increased from PWM frequency from 10 kHz?

Regards,

U-SK

  • 0
    TI__Genius 10440 points
    Hi,

    I have asked for some assistance on the first question, I will let you know what I find out.

    On the second question, we benchmarked the previous version of the Motor Control demo here: www.ti.com/.../tidu701

    Section 7 discusses the benchmark results that we have for the motor control only demo (no EtherCAT in these numbers). From the table it appears that the A9 takes around ~7us to switch context (interrupt latency) and then perform the FOC loop calculation. The rest of the time should be left for EtherCAT operation and other application level functionality.

    What is the PWM cycle time that you would like to achieve? Assuming a 16kHz PWM cycle time there would still be ~55us left in each cycle for other functions. 32kHz would leave ~24us per cycle.

    Jason Reeder
  • 0 in reply to Jason Reeder
    TI__Mastermind 43296 points
    Hi U-SK,

    To the first question on PRU-ICSS 1 and A 9 operate synchronization:

    From the EtherCAT stack point of view, the process data synchronization is handled by syncManager (SM), see the details of SM in the EtherCAT Communication Principle document from ETG at www.ethercat.org/.../downloads_4A8B20A0EDC348888CC85417677A359F.htm

    The implementation of SM and process data access on Sitara is interrupt based and as the followings:

    For Process Data Output: Application buffer is copied from SM buffer in ICSS memory/ESC DPRAM
    - Application reads the pointer to read
    - Invoked from PDI_Isr/Sync0_Isr/MainLoop
    - Call sequence: PDO_OutputMapping=>HW_EscReadIsr

    For Process Data Input: Application buffer is copied to SM buffer in ICSS memory/ESC DPRAM
    - Application reads the pointer to write
    - Invoked from PDI_Isr/Sync0_Isr/MainLoop
    - Call sequence: PDO_InputMapping=>HW_EscWriteIsr

    The interrupt mapping is implemented in tiesc_pruss_intc_mapping.h.

    Regards,
    Garrett