• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 98 subscribers
  • Views 488 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA80M: Access to WKUP_GPIO via MCU and Main domain

Thorsten Lorenzen
Genius 17101 points

Part Number: DRA80M

Gents, 

I can't really find answer in TRM. 

The Connectivity Matrix states Masters having access to various slaves (e.g. WKUP_GPIO). What is the Master name for MCU (R5F core) to access WKUP_GPIOs?

Would the Main domain even have access to WKUP_GPIOs (e.g. A53 core)?

What is Master name if so?

Please point to sections in TRM for understanding. 

Many thanks

Thorsten

  • 0
    TI__Expert 4885 points

    Hi, ,

    The master name of MCU (R5F cores) is MCU_ARMSS0_P0 (for CPU0) and MCU_ARMSS0_P1 (for CPU1).

    A53 master accesses CBASS0 through master ports -  NAVSS_LO and NAVSS_HI via MSMC as it is written in .

    According to WKUP_CBASS0 Connectivity Matrix table,  A53 has access to WKUP_GPIO through these two master ports. There is no more information in TRM where I can point to.

    ,

    Please confirm the ports via which the A53 access CBASS0.

    Regards,

    Mariya

  • 0 in reply to Mariya Petkova
    TI__Genius 17101 points
    Hi Mariya,
    many thanks for your response. Very helpful.

    Please take note, due to "connectivity matrix" MCU_ARMSS0_P0 and MCU_ARMSS0_P1 would have no access to any WKUP_CBASS0 slave. No GPIO, nor others. That doesn't make sense. This may be a misprint as I have doubts MCU can't access WKUP domain nor Main domain.

    Can you please verify?

    Many thanks,
    Thorsten
  • 0 in reply to Thorsten Lorenzen
    TI__Expert 4885 points
    Hi, ,

    Sorry, for the late response. I've just received the confirmation about the A53 master port:
    "All the transactions from A53 to SoC level goes through navss256l.main_0.nav_mst_lo master port. Therefore, A53 has full accessibility to all the SoC level slave end point."

    Still investigating the R5F access. Will post immediately when I have response.

    Regards,
    Mariya
  • 0 in reply to Mariya Petkova
    TI__Expert 4885 points
    Hi, ,

    Again, very sorry for the late response. Due to the holiday the response came late.

    About R5 I received the following answer:
    "R5 has multiple sets of master interfaces. Inside R5 subsystem, it does address decoding to distribute the transactions among those master interfaces before they are sent to the rest of SoC. Therefore, if one slave end point is accessed by one master interface of R5, then the other master interface of R5 will not have access to that same slave end point.

    From the user perspective, R5 has full accessibility of everything memory mapped on the SoC level, except its own ATCB/BTCM ( because R5 has access to its own ATCM/BTCM internally)."

    Regards,
    Mariya