AM3352: Am3352 GPMC interfacing & memory mapping

Manoj Prabhakar27

Part Number: AM3352

Hi Team,

In the AM3352 processor architecture through the GPMC interface i have parallely connected the NVSRAM and FPGA , please check and tell me whether the connections are ok and i need to know whether it will affect memory mapping.i'm attaching the block diagram and the schematic of the am3352 , please review and give your comments.

Thanks & regards

Manoj prabhakar

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

What is the Reason for these bidirectional buffers? SYSBOOT pins isolation?

0 Manoj Prabhakar27 over 7 years ago in reply to Biser Gatchev-XID

Intellectual 470 points

Hi,

The bi directional buffers not used for SYSBOOT isolation. Its for application purpose only.
we are plan to connect NVSRAM and FPGA in non-muxed mode .NVSRAM have 18 address lines and 16-bit data lines.For FPGA 16-bit address and 16-bit data.i need to know whether this configuration applicable or not.please give your comments.

Thanks & regards

Manoj prabhakar

0 Biser Gatchev-XID over 7 years ago in reply to Manoj Prabhakar27

TI__Guru**** 393215 points

Yes, this is a valid configuration. However you must make sure that the SYSBOOT signals, which are on pins LCD_DATA[15:0], do not get driven by external signals (FPGA or SRAm in your case) at PORZ release time.

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AM3352: Am3352 GPMC interfacing & memory mapping