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DM648 cache coherency problem

Isara
Intellectual 1130 points
I have a customer who migrate their code from DM642 to DM648. We are seeing a strange behavior of cache controller problem. According to the cache user guide and megamodule reference guide, cache controller will automatically take care of data coherency for EDMA data traffic to L2 SRAM. This is also true in DM642 (C64x core).  Customer code implement the same task on DM642 and works fine, when they are trying to do the same code in the DM648 it does not work.  It appears that the DM648’s L1 cache is the problem and they solve it by invalidating L1 cache. Is this a bug? e.g. this does not work 1)      Get some data in external memory2)      QDMA from external memory to IRAM3)      Wait for QDMA completion4)      Look at IRAM to see if data is available But this does work 1)      Get some data in external memory2)      Invalidate L1 cache3)      QDMA from external memory to IRAM4)      Wait for QDMA completion5)      Look at IRAM Regards,Isara 
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    TI__Guru*** 125430 points

    There's no (known) cache coherence issue when using internal memory.  I've written applications on other devices (e.g. 6455) where the EDMA was writing into L2 SRAM and I never had any issues with coherence.

    So if they're using QDMA, what's in the buffer in external memory?  That is, how was that buffer initialized?  If they used the CPU to initialize the buffer in external memory then they must perform a writeback before kicking off their QDMA transfer.  In your second set of steps, are you sure they're doing an "invalidate" and not a "writeback-invalidate"?  If they're doing a writeback-invalidate that would coincide with my theory...