• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 483 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM6437 VPBE LCD resolution

Guy
Intellectual 290 points

I want to interface some kind of LCD on the DM6437 but I don't know which resolution it support for its digital output.

What is the maximum resolution that could be use on it  for a 60 Hz refresh rate ? 

Guy

 

  • 0
    TI__Guru 64500 points

    Guy said:

    What is the maximum resolution that could be use on it  for a 60 Hz refresh rate?


    The DM6437 VPBE (Video Port Back End) supports a 13.33ns pixel clock period, or ~75MHz frequency.  The refresh rate can be calculated based on the LCD characteristic requirements with the following formulae.  This is strictly speaking from an interface perspective.  Implications on memory bandwidth will also impact what you will be able to realize when factoring other operations as well as the number of bits per pixel.

    The LCD characteristics include Horizontal resolution, Horizontal front porch, Horizontal back porch, HSYNC pulse width (in terms of clock cycles), Vertical resolution, Vertical front porch, Vertical back porch, VSYNC pulse width and progressive versus interlaced.

    PCLK    : Pixel Clock Frequency
    HRES    : Horizontal resolution (in pixels)
    HFP      : Horizontal front porch (in pixel clocks)
    HBP      : Horizontal back porch (in pixel clocks)
    VRES    : Vertical resolution (in pixels)
    VFP      : Vertical front porch (in pixel clocks)
    VBP     : Vertical back portch (in pixel clocks)

    Progressive
    Refresh Rate =  PCLK / ((HRES + HFP + HBP + HSYNC) * (VRES + VFP + VBP + VSYNC))

    Interlaced
    Refresh Rate = PCLK / ((HRES + HFP + HBP + HSYNC) * (VRES + 2*(VFP + VBP + VSYNC))) 

     

    The above assumes the entire pixel data is transmitted in one pixel clock.  If the particular interface requires multiple clocks to transmit the pixel data, then this needs to be factored into the equations and will affect the refresh rate achievable. 

    The Video Port Back End User's Guide (SPRU952) will have the above parameters expressed in a slightly different way, but I referenced the parameters above as they might be described in a display datasheet.

     

  • 0 in reply to BrandonAzbell
    Prodigy 10 points

    hI Brandon

    Im triyng to Implemnet an YCC 8 bit digital output ,50 Hz output on the VPBE on 6437 . can you help me configure the VPBE register ? is it possoble at all ?

     

    Best regards

    Nimrod Streit 

  • 0 in reply to Nimrod Streit
    TI__Genius 14405 points

    Nimrod,

    What you want is feasible. However, this is considered as a nonstandard usage mode, and the setting depends on the blanking interval and several other factors. I would recommend you first understand what exactly the overall frame looks like, and then study the VPBE user guide (especially table65, figure 25, and section 4.4.4.4)