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C6747 EDMA3 with cslr

Lian
Intellectual 370 points

  Now, I just want to complete a very simple data transfer from 'xmt '  to 'rcv'  with EDMA3. I don't use the DSP BIOS, just use  the CSLr. I use DMA chanell , not QDMA chanell.

  Question:  After running the code, the data don't transfer from 'xmt' to 'rcv'.
         Q1. After Step 5, I don't see any change in register ESR. Is this right? Has EVENT1 been triggered?
             and the edma3ccRegs->EMR is 0. It is said that no event is missed .
         Q2. Is there any error among the settings?

And I set the Register as follow: 

1.Writing into EESR, enable the EVENT 1;
2.Set up DMAQNUM to map the EVENT 1 to the  Queue 0;
3.Parameter set setup. chanell 1-->PARAMSET[1];
   a)Channel Options Parameters----OPT----Transfer complete interrupt is disabled. And A-synchronized;
   b)Channel Source Address Parameter---SRC----&xmt;
   c)A Count/B Count Parameter---A_B_CNT----ACNT=N=10; BCNT=1;
   d)Channel Destination Address---DST----&rcv;
   e)Source B Index/Destination B Index Parameter--- SRC_DST_BIDX---DSTBIDX=0;SRCBIDX=0; 
   f)Link Address/B Count Reload Parameter---LINK_BCNTRLD--- BCNTRLD=1; LINK=Parameters Set 1 Byte address;
   g)SRC_DST_CIDX---DSTCIDX=0;SRCCIDX=0;
   h)CCNT=1;
4.Disable the interrupt in IER by writing 0 to IESR.
5.Manually-triggered EVENT1 by writing 0x0002 to  ESR.
6.Wait for completion.

The code as follows,
 edma3ccRegs->EESR |= (Uint32) 0x0002;
 edma3ccRegs->DMAQNUM[0] =  (CSL_EDMA3CC_DMAQNUM_E1_Q0 << CSL_EDMA3CC_DMAQNUM_E1_SHIFT);
 edma3ccRegs->PARAMSET[1].OPT = (CSL_EDMA3CC_OPT_TCINTEN_DISABLE << CSL_EDMA3CC_OPT_TCINTEN_SHIFT)|\
           (CSL_EDMA3CC_OPT_SYNCDIM_ASYNC << CSL_EDMA3CC_OPT_SYNCDIM_SHIFT);
 edma3ccRegs->PARAMSET[1].SRC = (Uint32) &xmt;
 edma3ccRegs->PARAMSET[1].A_B_CNT = (Uint32) 0x0001000A;
 edma3ccRegs->PARAMSET[1].DST = (Uint32) &rcv;
 edma3ccRegs->PARAMSET[1].SRC_DST_BIDX = (0x0000 << CSL_EDMA3CC_SRC_DST_BIDX_DSTBIDX_SHIFT)|\    

      (0x0000 << CSL_EDMA3CC_SRC_DST_BIDX_SRCBIDX_SHIFT);
 edma3ccRegs->PARAMSET[1].LINK_BCNTRLD = 0x00014020;
 edma3ccRegs->PARAMSET[1].SRC_DST_CIDX = (Uint32)0x00;
 edma3ccRegs->PARAMSET[1].CCNT = (Uint32)0x01;
        edma3ccRegs->IESR =0x00;
        edma3ccRegs->ESR |= (Uint32) 0x0002;
 while(!(edma3ccRegs->IPR & 0x0002));

  • 0
    TI__Guru*** 125430 points

    Lian said:
     edma3ccRegs->PARAMSET[1].OPT = (CSL_EDMA3CC_OPT_TCINTEN_DISABLE << CSL_EDMA3CC_OPT_TCINTEN_SHIFT)|\
               (CSL_EDMA3CC_OPT_SYNCDIM_ASYNC << CSL_EDMA3CC_OPT_SYNCDIM_SHIFT);

    You need to set TCINTEN=1 and TCC=1 (since you later poll bit 1 for completion).

     

    Lian said:
     edma3ccRegs->PARAMSET[1].SRC = (Uint32) &xmt;
     edma3ccRegs->PARAMSET[1].A_B_CNT = (Uint32) 0x0001000A;
     edma3ccRegs->PARAMSET[1].DST = (Uint32) &rcv;

    If xmt and rcv are in internal memory make sure your linker command file defines L2, etc as being 0x11800000 (not 0x00800000 which is only CPU accessible).

  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points

    Brad Griffis said:
    If xmt and rcv are in internal memory make sure your linker command file defines L2, etc as being 0x11800000 (not 0x00800000 which is only CPU accessible).

    For more details please see the section "Incorrect Linker Command File" in this wiki page.  I put a more complete explanation there.

  • 0 in reply to Brad Griffis
    Intellectual 370 points

    Thanks for your reply. I have modified my code as you said.

    a.Set TCINTEN=1 and TCC=2.

    b.Define L2 begin at 0x11800000.

    After that, I'm very glad tosee the data begin to transfer from xmt to rcv. However, the data didn't transfer entirely. I set the ACNT=N=10.  From the Watch Window, I just see:

    and the xmt is as follows,

    As a result, the code is polling here all the time.

    while(!(edma3ccRegs->IPR & 0x0002));

    Can you give me any suggestion to this? And why the data didn't transfer entirely?

    Thank you very much!  O(∩_∩)O~

  • 0 in reply to Brad Griffis
    Intellectual 370 points

    Hi,I know why the data didn't tranfer entirely. That's because I set ACNT=10.  That means I want to transfer 10 Bytes=2.5*Uint32. But  in fact I want to transfer 10*32bits , equals to 40*8bits,so when I set the ACNT=0x28. The transfer succeed.

    In the mean time, I have another question.

    Although the transfer succeed. My running code is polling here.

     while(!(edma3ccRegs->IPR & 0x0002));

    That's because the IPR in the Watch Window which I saw is 4. Why not 2 ?

    Wish you reply as soon as possible!  Thank you!

  • 0 in reply to Lian
    TI__Guru*** 125430 points

    Whoops!  Sorry, we should be specifying TCC=1. (I've correct my earlier post.) The TCC field itself should be a number from 0-31 (i.e. 5-bit field).  This will cause the corresponding bit in IPR to be set.  So for example if we set TCC=5 then we would expect to see bit 5 set (1<<5).  So in your original case with TCC=2 we expect to see 1<<2 in IPR.

    Glad to see everything is working now!  Please click "Verify Answer" on my earlier post that contained the solution to your problem.  Thanks!