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66AK2H14: SPI sharing

Bruno B
Expert 1290 points
Part Number: 66AK2H14

HI,

We intend to build an SPI link (MOSI, MISO, CLK)  + CS0 to access an external peripheral. Nothing special to say about that , except that there will be also another SPI master on the same link. (we have mechanisms guaranteeing that SOC and 2nd SPI master will not try to access the peripheral during the same time slots)

Buffer barriers and multiplexers will be used in the CS, MOSI, and CLK paths in order to share the peripheral between the SOC and the 2nd SPI master. This guaranties that no electrical contentions will occur.

On the other hand, for PCB space saving  we don't plan any isolation in the MISO path.I don't see any electrical problem here, but this architecture means that the SOC will receive activity on its MISO input while its MOSI,CS, and CLK are inactive.

The question is : could this be a problem for the SOC ?

With best regards,

Bruno

  • 0
    TI__Mastermind 46460 points

    Bruno,

    I am not aware of any functional issues with the plan that you described.  However, this implementation is outside of the standard use case for SPI as it is a single-master bus.  Also, it is an implementation that is not qualified for this device.  Therefore, I cannot provide guarantees.

    Note that the bus switching may induce glitches on the signal lines.  These could cause issues with either the processor or the slave SPI devices.  This must be avoided in the implementation.

    Tom