Compiler/TDA3: TDA3x

chen

Part Number: TDA3

Tool/software: TI C/C++ Compiler

Hi,I have some questions about programing in tda3x

1.How should I use EDMA in tda3x,do you give some examples of the usage of edma for tda3x?

2.When I use C66x_DSPLIB in tda3x,I find out that the running cycle is different from the number given in the Cycle Benchmarks of <<Texas Instruments Test Results DSPLIB 3.4.0.0 C66x>>.

The time recorded for length of 128 DSPF_sp_fftSPxSP is 816,while in my case, the clock number is almost four times of that.All the data is in L2_SRAM. Can we use C66x_DSPLIB in tda3x and if we can,how should we make it the same clock as is described in the <<Texas Instruments Test Results DSPLIB 3.4.0.0 C66x>>.

Thank you!

over 6 years ago

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi Chen,

EDMA example is here: PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\csl\example\edma

Regards,
Rishabh

0 Yordan Kamenov over 6 years ago

TI__Mastermind 42515 points

Hi Chen,

for first question you can check if this helps:
processors.wiki.ti.com/.../PDK_TDA_CSL_User_Guide

(for second question DSPLIB experts will reply here soon)

Regards,
Yordan

0 Jesse Villarreal over 6 years ago in reply to Yordan Kamenov

TI__Expert 5555 points

If you are running the data from L2 SRAM, and you have the L1 cache configured for L2SRAM address range, I assume the difference with the performance number is due to L1 cache misses latency.

0 chen over 6 years ago in reply to Jesse Villarreal

Intellectual 430 points

Hi,I find the problem.I think I just put the code into the wrong place.When I put the code into L2_SRAM,it is almost the same.

0 Yordan Kamenov over 6 years ago in reply to chen

TI__Mastermind 42515 points

Hi Chen,

thanks for the update, I will close the thread.
If you have follow up questions feel free to write here and reopen it or create new thread.

Regards,
Yordan

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Compiler/TDA3: TDA3x