• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 691 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: Ecc error when performing WbInv

Shay Karuchi
Prodigy 220 points
Part Number: TMS320C6678


Hi,

We're enabling Ecc on some of DDR3 addresses. Additionally, enabled Ecc addresses are cached.

as part of our flow we need to perform a write back invalidate on part of these addresses.

i get there're 2 way to do it:

1.  write back invalidate for specific addresses - write the start address to CACHE_L2WIBAR (0x01844010), write word count to CACHE_L2WIWC (0x01844014) and wait for CACHE_L2WIWC  to equal 0.

2. write back invalidate to all L2 - write 1 to CACHE_L2WBINV (0x01845004).

when using the first method we get Ecc interrupt (Ecc write error). using the second method does not trigger Ecc interrupt.

 why is the interrupt triggerd an is it an expected behavior?

thanks,

shay.

  • 0
    TI__Mastermind 46460 points

    Shay,

    All writes to ECC protected regions must be 64-bit aligned and in even multiples of 8 bytes.  Please see section 2.17 in the KeyStone Architecture DDR3 Memory Controller User's Guide SPRUGV8.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    yeah I've noticed that. that's why i stated that the enabled Ecc addresses are cached. Since all cached addresses read/write are by default align to cach line size (128 bytes).
    And indeed in our code read/write to the Ecc enabled (cached) addresses are not aligned to 64 bit nor a multiple of 8 bytes, and still don't trigger the Ecc interrupt.

    the relevant problem is only when performing write back invalidate for specified addresses (rather than to all L2).

    shay.
  • 0 in reply to Shay Karuchi
    TI__Mastermind 46460 points

    Shay,

    You indicated that you are doing a write-back for cached contents that are not in a data type that is a multiple of 8-bytes and/or it is not 8-byte aligned.  You must use instructions that meet these requirements.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    Hi Tom,
    maybe i wasn't clear enough.
    i also tried to change the address and word count so that they will comply with 64bit aligned address and 8byte size demands.
    that didn't help also, the Ecc error still triggered.
    shay.
  • 0 in reply to Shay Karuchi
    TI__Mastermind 46460 points

    Shay,

    We believe that writes of 64-bit aligned quanta should be enough to prevent erroneous ECC error events.  DDR write ECC errors can only come on a sub quanta writes.

    Perhaps there is an unexpected behavior in the cache writebacks when using the method that you see fail.  Do you know if the cache line being written is dirty?  Is it possible that it contains contents that are not dirty?  Do you see this error on all cache writebacks or only on certain ones - which perhaps are only partially dirty?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    hi,
    i'm writing 1440 bytes to cached addresses (align to 64bits) and immediately after that perform writeback invalidate with the start address and 1440/4 (words) size, so all relevant cache lines should be dirty.
    (i also tried to perform the writeback invalidate with address and size that aligned to cach line size (128 bytes) but got the same result).

    shay.