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whether EMIF SRE signal function, when EDMA source is a FIFO on 32 bits/sync EMIF (EDMA is AB sync, Acnt=4)

houdp
Prodigy 20 points

Hello,

We meet a EDMA-EMIF-FIFO issue on C6454, could you give some explanation?

My system: FPGA<----32bits/Sync EMIF--->DSP

The EMIF timing during EDMA trans is attached.

EMIF config:

CE3 CE3CFG: 32bits, sync, CE_EXT=1, RD_BE_EN=1, R_ENABLE=1, W_LTNCY_ZEROCYCLE, R_LTNCY_THREECYCLE

EDMA paramset: 

src: 32bits FIFO on CE3 with 64bytes aligned address, dst: ddr, AB sync, acnt=4, bcnt=1000, ccnt=1, bSrcIndex=0, SAM=DAM=INCR,

In FPGA side, CE3, EA, SOE, ECLKOUT pins work together for data output to EMIF. SRE is not used in fpga for data out.

Result:

When Acnt=4,2,1, every eight 32bits words, one 32bits is lost during EDMA trans. When Acnt=8,16,32, … data receiving is ok.

We also found that:

  1. EDMA Acnt<=4, EMIF address pin is constant. Acnt>4, EMIF address pin changed alternantly。
  2. When EDMA Acnt is 4 and EMIF read latency is 3, EMIF SRE signal is asserted every eight 32bits words, and data lost happened. When Acnt=8, read latency is 3, SRE signal didn’t work during EDMA, and data rx is ok.
  3. When Acnt=4, read latency is 2 or 1, SRE was not asserted during EDMA, and data not lost.

 

 

Our question is:

  1. Could you explain the test result?

    2.  Whether SRE signal must be used for EMIF transmission in FPGA side, when EDMA-EMIF-FIFO works in AB sync mode?

  • 0
    TI__Guru* 84110 points

    Does your interface to the FPGA FIFO work correctly if you use DSP code to do the reads? It would be best to start there to make sure you have a known working interface before moving to the bursting transfers with the EDMA.

    I assume you can look at the waveforms on the EMIF, since you can tell that SRE is being asserted.

    Can you compare the waveforms to the diagrams shown in the datasheet and/or EMIF User's Guide? Does it appear that the timing you expect is being delivered on the EMIF?

    With the EDMA-based operation, can you compare the data being transferred in the waveforms to the data expected to be transferred?

    What is lost when data is lost? First of a burst, last of a burst, etc.?

  • 0 in reply to RandyP
    Prodigy 20 points

    Hello Randy,

    Thanks for the reply.

    What I have tried:

    1. EMIF-32bits FIFO software read - ok.

    2. EMIF-32bits FIFO EDMA Asnyc mode read - ok.

    3. EMIF-32bits FIFO EDMA Snyc mode AxB=1,2,4*1000 read - fail.

    4. EMIF-32bits FIFO EDMA Snyc mode AxB=8,16,32*1000 read - ok.

     

    ECLKOUT, CE, address and  SOE pins are used for EMIF signal interpretation in FPGA, SRE signal is not used.

    One 32 bits words lost in DSP every eight 32bits burst transfer.

    SRE signal function is not described clear in EMIF spec.

    I want to know the exact usage for SRE signal when EMIF working in sync FIFO EDMA read mode.

    I missed the timing figure in last message. I attach it here for your reference.

     

    Best regards,

    houdp

    GE healthcare

    8306.EMIF_timing_EDMA_FIFO_read.zip

     

     

  • 0 in reply to houdp
    TI__Guru* 84110 points

    houdp,

    This has been sitting open for a long time. I had hoped someone who can accurately describe SRE's use would have answered you.

    Looking at your timing diagrams and the odd addressing, I am curious about the exact settings in your PaRAM.

    If you have solved this and moved on, we are all very glad for you.

    If not, would you please send the hex values for the 8 PaRAM registers prior to initiating the transfers, for each of the EDMA modes?

    Regards,
    RandyP